from nmigen import Module, Signal, Mux
from nmigen.compat.sim import run_simulation
+from nmigen.cli import verilog, rtlil
+
from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
from example_buf_pipe import ExampleCombPipe, CombPipe
-from example_buf_pipe import IOAckIn, IOAckOut
+from example_buf_pipe import PrevControl, NextControl
from random import randint
def check_o_n_valid(dut, val):
- o_n_valid = yield dut.o.n_valid
+ o_n_valid = yield dut.n.o_valid
assert o_n_valid == val
def testbench(dut):
#yield dut.i_p_rst.eq(1)
- yield dut.i.n_ready.eq(0)
- yield dut.o.p_ready.eq(0)
+ yield dut.n.i_ready.eq(0)
+ yield dut.p.o_ready.eq(0)
yield
yield
#yield dut.i_p_rst.eq(0)
- yield dut.i.n_ready.eq(1)
- yield dut.i.data.eq(5)
- yield dut.i.p_valid.eq(1)
+ yield dut.n.i_ready.eq(1)
+ yield dut.p.i_data.eq(5)
+ yield dut.p.i_valid.eq(1)
yield
- yield dut.i.data.eq(7)
+ yield dut.p.i_data.eq(7)
yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed
yield
yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
- yield dut.i.data.eq(2)
+ yield dut.p.i_data.eq(2)
yield
- yield dut.i.n_ready.eq(0) # begin going into "stall" (next stage says ready)
- yield dut.i.data.eq(9)
+ yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
+ yield dut.p.i_data.eq(9)
yield
- yield dut.i.p_valid.eq(0)
- yield dut.i.data.eq(12)
+ yield dut.p.i_valid.eq(0)
+ yield dut.p.i_data.eq(12)
yield
- yield dut.i.data.eq(32)
- yield dut.i.n_ready.eq(1)
+ yield dut.p.i_data.eq(32)
+ yield dut.n.i_ready.eq(1)
yield
yield from check_o_n_valid(dut, 1) # buffer still needs to output
yield
def testbench2(dut):
- #yield dut.i.p_rst.eq(1)
- yield dut.i.n_ready.eq(0)
- #yield dut.o.p_ready.eq(0)
+ #yield dut.p.i_rst.eq(1)
+ yield dut.n.i_ready.eq(0)
+ #yield dut.p.o_ready.eq(0)
yield
yield
- #yield dut.i.p_rst.eq(0)
- yield dut.i.n_ready.eq(1)
- yield dut.i.data.eq(5)
- yield dut.i.p_valid.eq(1)
+ #yield dut.p.i_rst.eq(0)
+ yield dut.n.i_ready.eq(1)
+ yield dut.p.i_data.eq(5)
+ yield dut.p.i_valid.eq(1)
yield
- yield dut.i.data.eq(7)
+ yield dut.p.i_data.eq(7)
yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed 2 clocks
yield
yield from check_o_n_valid(dut, 0) # effects of i_p_valid delayed 2 clocks
- yield dut.i.data.eq(2)
+ yield dut.p.i_data.eq(2)
yield
yield from check_o_n_valid(dut, 1) # ok *now* i_p_valid effect is felt
- yield dut.i.n_ready.eq(0) # begin going into "stall" (next stage says ready)
- yield dut.i.data.eq(9)
+ yield dut.n.i_ready.eq(0) # begin going into "stall" (next stage says ready)
+ yield dut.p.i_data.eq(9)
yield
- yield dut.i.p_valid.eq(0)
- yield dut.i.data.eq(12)
+ yield dut.p.i_valid.eq(0)
+ yield dut.p.i_data.eq(12)
yield
- yield dut.i.data.eq(32)
- yield dut.i.n_ready.eq(1)
+ yield dut.p.i_data.eq(32)
+ yield dut.n.i_ready.eq(1)
yield
yield from check_o_n_valid(dut, 1) # buffer still needs to output
yield
send = True
else:
send = randint(0, send_range) != 0
- o_p_ready = yield self.dut.o.p_ready
+ o_p_ready = yield self.dut.p.o_ready
if not o_p_ready:
yield
continue
if send and self.i != len(self.data):
- yield self.dut.i.p_valid.eq(1)
- yield self.dut.i.data.eq(self.data[self.i])
+ yield self.dut.p.i_valid.eq(1)
+ yield self.dut.p.i_data.eq(self.data[self.i])
self.i += 1
else:
- yield self.dut.i.p_valid.eq(0)
+ yield self.dut.p.i_valid.eq(0)
yield
def rcv(self):
stall_range = randint(0, 3)
for j in range(randint(1,10)):
stall = randint(0, stall_range) != 0
- yield self.dut.i.n_ready.eq(stall)
+ yield self.dut.n.i_ready.eq(stall)
yield
- o_n_valid = yield self.dut.o.n_valid
- i_n_ready = yield self.dut.i.n_ready
+ o_n_valid = yield self.dut.n.o_valid
+ i_n_ready = yield self.dut.n.i_ready
if not o_n_valid or not i_n_ready:
continue
- o_data = yield self.dut.o.data
+ o_data = yield self.dut.n.o_data
self.resultfn(o_data, self.data[self.o], self.i, self.o)
self.o += 1
if self.o == len(self.data):
send = True
else:
send = randint(0, send_range) != 0
- o_p_ready = yield self.dut.o.p_ready
+ o_p_ready = yield self.dut.p.o_ready
if not o_p_ready:
yield
continue
if send and self.i != len(self.data):
- yield self.dut.i.p_valid.eq(1)
+ yield self.dut.p.i_valid.eq(1)
for v in self.dut.set_input(self.data[self.i]):
yield v
self.i += 1
else:
- yield self.dut.i.p_valid.eq(0)
+ yield self.dut.p.i_valid.eq(0)
yield
def rcv(self):
stall_range = randint(0, 3)
for j in range(randint(1,10)):
stall = randint(0, stall_range) != 0
- yield self.dut.i.n_ready.eq(stall)
+ yield self.dut.n.i_ready.eq(stall)
yield
- o_n_valid = yield self.dut.o.n_valid
- i_n_ready = yield self.dut.i.n_ready
+ o_n_valid = yield self.dut.n.o_valid
+ i_n_ready = yield self.dut.n.i_ready
if not o_n_valid or not i_n_ready:
continue
- o_data = yield self.dut.o.data
+ o_data = yield self.dut.n.o_data
self.resultfn(o_data, self.data[self.o], self.i, self.o)
self.o += 1
if self.o == len(self.data):
while True:
stall = randint(0, 3) != 0
send = randint(0, 5) != 0
- yield dut.i.n_ready.eq(stall)
- o_p_ready = yield dut.o.p_ready
+ yield dut.n.i_ready.eq(stall)
+ o_p_ready = yield dut.p.o_ready
if o_p_ready:
if send and i != len(data):
- yield dut.i.p_valid.eq(1)
- yield dut.i.data.eq(data[i])
+ yield dut.p.i_valid.eq(1)
+ yield dut.p.i_data.eq(data[i])
i += 1
else:
- yield dut.i.p_valid.eq(0)
+ yield dut.p.i_valid.eq(0)
yield
- o_n_valid = yield dut.o.n_valid
- i_n_ready = yield dut.i.n_ready
+ o_n_valid = yield dut.n.o_valid
+ i_n_ready = yield dut.n.i_ready
if o_n_valid and i_n_ready:
- o_data = yield dut.o.data
+ o_data = yield dut.n.o_data
assert o_data == data[o] + 2, "%d-%d data %x not match %x\n" \
% (i, o, o_data, data[o])
o += 1
v v
i_p_valid >>in pipe1 o_n_valid out>> i_p_valid >>in pipe2
o_p_ready <<out pipe1 i_n_ready <<in o_p_ready <<out pipe2
- i_data >>in pipe1 o_data out>> i_data >>in pipe2
+ p_i_data >>in pipe1 p_i_data out>> n_o_data >>in pipe2
"""
def __init__(self):
self.pipe1 = ExampleBufPipe()
self.pipe2 = ExampleBufPipe()
# input
- self.i = IOAckIn()
- self.i.data = Signal(32) # >>in - comes in from the PREVIOUS stage
+ self.p = PrevControl()
+ self.p.i_data = Signal(32) # >>in - comes in from the PREVIOUS stage
# output
- self.o = IOAckOut()
- self.o.data = Signal(32) # out>> - goes out to the NEXT stage
+ self.n = NextControl()
+ self.n.o_data = Signal(32) # out>> - goes out to the NEXT stage
def elaborate(self, platform):
m = Module()
m.submodules.pipe2 = self.pipe2
# connect inter-pipe input/output valid/ready/data
- m.d.comb += self.pipe1.connect_next(self.pipe2)
+ m.d.comb += self.pipe1.connect_to_next(self.pipe2)
# inputs/outputs to the module: pipe1 connections here (LHS)
m.d.comb += self.pipe1.connect_in(self)
test = Test5(dut, test6_resultfn)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd")
+ ports = [dut.p.i_valid, dut.n.i_ready,
+ dut.n.o_valid, dut.p.o_ready] + \
+ list(dut.p.i_data) + [dut.n.o_data]
+ vl = rtlil.convert(dut, ports=ports)
+ with open("test_ltcomb_pipe.il", "w") as f:
+ f.write(vl)
+