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output less-than test to ilang
[ieee754fpu.git]
/
src
/
add
/
test_buf_pipe.py
diff --git
a/src/add/test_buf_pipe.py
b/src/add/test_buf_pipe.py
index b84a66042607551e122d3569d1f5e94f12aa27dc..e32e2d322bc87cab445f677d0067376ce0c6b5aa 100644
(file)
--- a/
src/add/test_buf_pipe.py
+++ b/
src/add/test_buf_pipe.py
@@
-1,5
+1,7
@@
from nmigen import Module, Signal, Mux
from nmigen.compat.sim import run_simulation
from nmigen import Module, Signal, Mux
from nmigen.compat.sim import run_simulation
+from nmigen.cli import verilog, rtlil
+
from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
from example_buf_pipe import ExampleCombPipe, CombPipe
from example_buf_pipe import PrevControl, NextControl
from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
from example_buf_pipe import ExampleCombPipe, CombPipe
from example_buf_pipe import PrevControl, NextControl
@@
-346,3
+348,10
@@
if __name__ == '__main__':
test = Test5(dut, test6_resultfn)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd")
test = Test5(dut, test6_resultfn)
run_simulation(dut, [test.send, test.rcv], vcd_name="test_ltcomb6.vcd")
+ ports = [dut.p.i_valid, dut.n.i_ready,
+ dut.n.o_valid, dut.p.o_ready] + \
+ list(dut.p.i_data) + [dut.n.o_data]
+ vl = rtlil.convert(dut, ports=ports)
+ with open("test_ltcomb_pipe.il", "w") as f:
+ f.write(vl)
+