update comments

[ieee754fpu.git] / src / add / test_fsm_experiment.py

diff --git a/src/add/test_fsm_experiment.py b/src/add/test_fsm_experiment.py
index 51476ccf4be50d74b503c861085c1c67cc08fef7..17cee24ebb4cb5e85cd49311140017912f4488df 100644 (file)
--- a/src/add/test_fsm_experiment.py
+++ b/src/add/test_fsm_experiment.py
@@ -2,28 +2,43 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Const, Cat
+from nmigen import Module, Signal, Const, Cat, Elaboratable
 from nmigen.cli import main, verilog, rtlil
 from nmigen.compat.sim import run_simulation
 
 
-from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPState
-from singlepipe import eq, SimpleHandshake, ControlBase
+from fpbase import FPNumIn, FPNumOut, FPOpIn, FPOpOut, FPBase, FPState
+from nmoperator import eq
+from singlepipe import SimpleHandshake, ControlBase
 from test_buf_pipe import data_chain2, Test5
 
 
-class FPDIV(FPBase):
+class FPDIV(FPBase, Elaboratable):
 
     def __init__(self, width):
         FPBase.__init__(self)
         self.width = width
 
-        self.in_a  = FPOp(width)
-        self.in_b  = FPOp(width)
-        self.out_z = FPOp(width)
+        self.p = FPOpIn(width)
+        self.n = FPOpOut(width)
+
+        self.p.data_i = self.ispec()
+        self.n.data_o = self.ospec()
 
         self.states = []
 
+    def ispec(self):
+        return Signal(self.width, name="a")
+
+    def ospec(self):
+        return Signal(self.width, name="z")
+
+    def setup(self, m, i):
+        m.d.comb += self.p.v.eq(i) # connect input
+
+    def process(self, i):
+        return self.n.v # return z output
+
     def add_state(self, state):
         self.states.append(state)
         return state
@@ -37,10 +52,12 @@ class FPDIV(FPBase):
         a = FPNumIn(None, self.width, False)
         z = FPNumOut(self.width, False)
 
-        m.submodules.in_a = a
+        m.submodules.p = self.p
+        m.submodules.n = self.n
+        m.submodules.a = a
         m.submodules.z = z
 
-        m.d.comb += a.v.eq(self.in_a.v)
+        m.d.comb += a.v.eq(self.p.v)
 
         with m.FSM() as fsm:
 
@@ -48,8 +65,8 @@ class FPDIV(FPBase):
             # gets operand a
 
             with m.State("get_a"):
-                res = self.get_op(m, self.in_a, a, "add_1")
-                m.d.sync += eq([a, self.in_a.ack], res)
+                res = self.get_op(m, self.p, a, "add_1")
+                m.d.sync += eq([a, self.p.ready_o], res)
 
             with m.State("add_1"):
                 m.next = "pack"
@@ -69,7 +86,7 @@ class FPDIV(FPBase):
             # put_z stage
 
             with m.State("put_z"):
-                self.put_z(m, z, self.out_z, "get_a")
+                self.put_z(m, z, self.n, "get_a")
 
         return m
 
@@ -78,40 +95,25 @@ class FPDIVPipe(ControlBase):
     def __init__(self, width):
         self.width = width
         self.fpdiv = FPDIV(width=width)
-        ControlBase.__init__(self, self)
-
-    def ispec(self):
-        return Signal(self.width, name="a")
-
-    def ospec(self):
-        return Signal(self.width, name="z")
-
-    def setup(self, m, i):
-        m.d.comb += self.fpdiv.in_a.v.eq(i) # connect input
-
-    def process(self, i):
-        return self.fpdiv.out_z.v # return z output
+        ControlBase.__init__(self, self.fpdiv)
 
     def elaborate(self, platform):
-        self.m = m = ControlBase._elaborate(self, platform)
+        self.m = m = ControlBase.elaborate(self, platform)
 
         m.submodules.fpdiv = self.fpdiv
 
         # see if connecting to stb/ack works
-        m.d.comb += self.p.o_ready.eq(self.fpdiv.in_a.ack)
-        m.d.comb += self.fpdiv.in_a.stb.eq(self.p.i_valid_test)
-
-        m.d.comb += self.n.o_valid.eq(self.fpdiv.out_z.stb)
-        m.d.comb += self.fpdiv.out_z.ack.eq(self.n.i_ready_test)
-        m.d.comb += self.n.o_data.eq(self.fpdiv.out_z.v)
+        m.d.comb += self.fpdiv.p._connect_in(self.p)
+        m.d.comb += self.fpdiv.n._connect_out(self.n, do_data=False)
+        m.d.comb += self.n.data_o.eq(self.data_r)
 
         return m
 
-def resultfn(o_data, expected, i, o):
+def resultfn(data_o, expected, i, o):
     res = expected + 1
-    assert o_data == res, \
+    assert data_o == res, \
                 "%d-%d received data %x not match expected %x\n" \
-                % (i, o, o_data, res)
+                % (i, o, data_o, res)
 
 
 if __name__ == "__main__":