# Copyright (C) Jonathan P Dawson 2013
# 2013-12-12
-from nmigen import Module, Signal, Const, Cat
+from nmigen import Module, Signal, Const, Cat, Elaboratable
from nmigen.cli import main, verilog, rtlil
from nmigen.compat.sim import run_simulation
from fpbase import FPNumIn, FPNumOut, FPOpIn, FPOpOut, FPBase, FPState
-from singlepipe import eq, SimpleHandshake, ControlBase
+from nmoperator import eq
+from singlepipe import SimpleHandshake, ControlBase
from test_buf_pipe import data_chain2, Test5
-class FPDIV(FPBase):
+class FPDIV(FPBase, Elaboratable):
def __init__(self, width):
FPBase.__init__(self)
self.width = width
- self.in_a = FPOpIn(width)
- self.in_b = FPOpIn(width)
- self.out_z = FPOpOut(width)
+ self.p = FPOpIn(width)
+ self.n = FPOpOut(width)
+
+ self.p.data_i = self.ispec()
+ self.n.data_o = self.ospec()
self.states = []
+ def ispec(self):
+ return Signal(self.width, name="a")
+
+ def ospec(self):
+ return Signal(self.width, name="z")
+
+ def setup(self, m, i):
+ m.d.comb += self.p.v.eq(i) # connect input
+
+ def process(self, i):
+ return self.n.v # return z output
+
def add_state(self, state):
self.states.append(state)
return state
a = FPNumIn(None, self.width, False)
z = FPNumOut(self.width, False)
- m.submodules.in_a = a
+ m.submodules.p = self.p
+ m.submodules.n = self.n
+ m.submodules.a = a
m.submodules.z = z
- m.d.comb += a.v.eq(self.in_a.v)
+ m.d.comb += a.v.eq(self.p.v)
with m.FSM() as fsm:
# gets operand a
with m.State("get_a"):
- res = self.get_op(m, self.in_a, a, "add_1")
- m.d.sync += eq([a, self.in_a.ready_o], res)
+ res = self.get_op(m, self.p, a, "add_1")
+ m.d.sync += eq([a, self.p.ready_o], res)
with m.State("add_1"):
m.next = "pack"
# put_z stage
with m.State("put_z"):
- self.put_z(m, z, self.out_z, "get_a")
+ self.put_z(m, z, self.n, "get_a")
return m
def __init__(self, width):
self.width = width
self.fpdiv = FPDIV(width=width)
- ControlBase.__init__(self, self)
-
- def ispec(self):
- return Signal(self.width, name="a")
-
- def ospec(self):
- return Signal(self.width, name="z")
-
- def setup(self, m, i):
- m.d.comb += self.fpdiv.in_a.v.eq(i) # connect input
-
- def process(self, i):
- return self.fpdiv.out_z.v # return z output
+ ControlBase.__init__(self, self.fpdiv)
def elaborate(self, platform):
- self.m = m = ControlBase._elaborate(self, platform)
+ self.m = m = ControlBase.elaborate(self, platform)
m.submodules.fpdiv = self.fpdiv
# see if connecting to stb/ack works
- m.d.comb += self.p.ready_o.eq(self.fpdiv.in_a.ready_o)
- m.d.comb += self.fpdiv.in_a.valid_i.eq(self.p.valid_i_test)
-
- m.d.comb += self.n.valid_o.eq(self.fpdiv.out_z.valid_o)
- m.d.comb += self.fpdiv.out_z.ready_i.eq(self.n.ready_i_test)
- m.d.comb += self.n.o_data.eq(self.fpdiv.out_z.v)
+ m.d.comb += self.fpdiv.p._connect_in(self.p)
+ m.d.comb += self.fpdiv.n._connect_out(self.n, do_data=False)
+ m.d.comb += self.n.data_o.eq(self.data_r)
return m
-def resultfn(o_data, expected, i, o):
+def resultfn(data_o, expected, i, o):
res = expected + 1
- assert o_data == res, \
+ assert data_o == res, \
"%d-%d received data %x not match expected %x\n" \
- % (i, o, o_data, res)
+ % (i, o, data_o, res)
if __name__ == "__main__":