update comments

[ieee754fpu.git] / src / add / test_inout_mux_pipe.py

diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py
index a51ccf1ae0cbeb39e357516582569588df3d394c..35abe2eaf46b3aa148826b6821640cf39dfe2786 100644 (file)
--- a/src/add/test_inout_mux_pipe.py
+++ b/src/add/test_inout_mux_pipe.py
@@ -67,9 +67,9 @@ class InputTest:
             op2 = self.di[mid][i]
             rs = dut.p[mid]
             yield rs.valid_i.eq(1)
-            yield rs.i_data.data.eq(op2)
-            yield rs.i_data.idx.eq(i)
-            yield rs.i_data.mid.eq(mid)
+            yield rs.data_i.data.eq(op2)
+            yield rs.data_i.idx.eq(i)
+            yield rs.data_i.mid.eq(mid)
             yield
             o_p_ready = yield rs.ready_o
             while not o_p_ready:
@@ -113,9 +113,9 @@ class InputTest:
             if not o_n_valid or not i_n_ready:
                 continue
 
-            out_mid = yield n.o_data.mid
-            out_i = yield n.o_data.idx
-            out_v = yield n.o_data.data
+            out_mid = yield n.data_o.mid
+            out_i = yield n.data_o.idx
+            out_v = yield n.data_o.data
 
             print ("recv", out_mid, out_i, hex(out_v))
 
@@ -158,8 +158,8 @@ class OutputTest:
             mid = self.di[i][1]
             rs = dut.p
             yield rs.valid_i.eq(1)
-            yield rs.i_data.data.eq(op2)
-            yield rs.i_data.mid.eq(mid)
+            yield rs.data_i.data.eq(op2)
+            yield rs.data_i.mid.eq(mid)
             yield
             o_p_ready = yield rs.ready_o
             while not o_p_ready: