update comments

[ieee754fpu.git] / src / add / test_inputgroup.py

diff --git a/src/add/test_inputgroup.py b/src/add/test_inputgroup.py
index bb68861cbbe2cb155e906e55e1800fa123bc6ad9..09a72e176179e66d94484eebd5b971b2d3566d5a 100644 (file)
--- a/src/add/test_inputgroup.py
+++ b/src/add/test_inputgroup.py
@@ -3,7 +3,7 @@ from nmigen import Module, Signal
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from nmigen_add_experiment import InputGroup
+from inputgroup import InputGroup
 
 
 def testbench(dut):
@@ -130,7 +130,7 @@ class InputTest:
             yield rs.stb.eq(0)
 
             # wait random period of time before queueing another value
-            for i in range(randint(0, 12)):
+            for i in range(randint(0, 8)):
                 yield
 
     def recv(self):
@@ -138,10 +138,10 @@ class InputTest:
             stb = yield dut.out_op.stb
             yield dut.out_op.ack.eq(0)
             while not stb:
+                yield dut.out_op.ack.eq(1)
                 yield
                 stb = yield dut.out_op.stb
 
-            yield dut.out_op.ack.eq(1)
             stb = yield dut.out_op.stb
             while stb:
                 yield