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[ieee754fpu.git]
/
src
/
add
/
test_inputgroup.py
diff --git
a/src/add/test_inputgroup.py
b/src/add/test_inputgroup.py
index e78090ea69fc4192422832ef9dbc04220fc67f33..09a72e176179e66d94484eebd5b971b2d3566d5a 100644
(file)
--- a/
src/add/test_inputgroup.py
+++ b/
src/add/test_inputgroup.py
@@
-3,7
+3,7
@@
from nmigen import Module, Signal
from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
-from
nmigen_add_experiment
import InputGroup
+from
inputgroup
import InputGroup
def testbench(dut):