update comments

[ieee754fpu.git] / src / add / test_syncops.py

diff --git a/src/add/test_syncops.py b/src/add/test_syncops.py
index c413322b971a3d47b70514acb243b8f7a832c56e..484597ca9058cb1998047636b80e003f16fe9f05 100644 (file)
--- a/src/add/test_syncops.py
+++ b/src/add/test_syncops.py
@@ -3,7 +3,7 @@ from nmigen import Module, Signal
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog
 
-from nmigen_add_experiment import FPGetSyncOpsMod
+from inputgroup import FPGetSyncOpsMod
 
 
 def testbench(dut):