update comments

[ieee754fpu.git] / src / add / unit_test_single.py

diff --git a/src/add/unit_test_single.py b/src/add/unit_test_single.py
index c0601288a0edb345874328c785dc9eb075a2c5da..2b0d9e569e2a86d3382ef17579fc62cf63fa835e 100644 (file)
--- a/src/add/unit_test_single.py
+++ b/src/add/unit_test_single.py
@@ -41,35 +41,35 @@ def get_rs_case(dut, a, b, mid):
     out_z = dut.res[0]
     yield dut.ids.in_mid.eq(mid)
     yield in_a.v.eq(a)
-    yield in_a.stb.eq(1)
+    yield in_a.valid_i.eq(1)
     yield
     yield
     yield
     yield
-    a_ack = (yield in_a.ack)
+    a_ack = (yield in_a.ready_o)
     assert a_ack == 0
 
-    yield in_a.stb.eq(0)
+    yield in_a.valid_i.eq(0)
 
     yield in_b.v.eq(b)
-    yield in_b.stb.eq(1)
+    yield in_b.valid_i.eq(1)
     yield
     yield
-    b_ack = (yield in_b.ack)
+    b_ack = (yield in_b.ready_o)
     assert b_ack == 0
 
-    yield in_b.stb.eq(0)
+    yield in_b.valid_i.eq(0)
 
-    yield out_z.ack.eq(1)
+    yield out_z.ready_i.eq(1)
 
     while True:
-        out_z_stb = (yield out_z.stb)
+        out_z_stb = (yield out_z.valid_o)
         if not out_z_stb:
             yield
             continue
         vout_z = yield out_z.v
         #out_mid = yield dut.ids.out_mid
-        yield out_z.ack.eq(0)
+        yield out_z.ready_i.eq(0)
         yield
         break
 
@@ -87,35 +87,35 @@ def check_rs_case(dut, a, b, z, mid=None):
 def get_case(dut, a, b, mid):
     #yield dut.in_mid.eq(mid)
     yield dut.in_a.v.eq(a)
-    yield dut.in_a.stb.eq(1)
+    yield dut.in_a.valid_i_test.eq(1)
     yield
     yield
     yield
     yield
-    a_ack = (yield dut.in_a.ack)
+    a_ack = (yield dut.in_a.ready_o)
     assert a_ack == 0
 
-    yield dut.in_a.stb.eq(0)
+    yield dut.in_a.valid_i.eq(0)
 
     yield dut.in_b.v.eq(b)
-    yield dut.in_b.stb.eq(1)
+    yield dut.in_b.valid_i.eq(1)
     yield
     yield
-    b_ack = (yield dut.in_b.ack)
+    b_ack = (yield dut.in_b.ready_o)
     assert b_ack == 0
 
-    yield dut.in_b.stb.eq(0)
+    yield dut.in_b.valid_i.eq(0)
 
-    yield dut.out_z.ack.eq(1)
+    yield dut.out_z.ready_i.eq(1)
 
     while True:
-        out_z_stb = (yield dut.out_z.stb)
+        out_z_stb = (yield dut.out_z.valid_o)
         if not out_z_stb:
             yield
             continue
         out_z = yield dut.out_z.v
         #out_mid = yield dut.out_mid
-        yield dut.out_z.ack.eq(0)
+        yield dut.out_z.ready_i.eq(0)
         yield
         break
 
@@ -141,7 +141,6 @@ def run_test(dut, stimulus_a, stimulus_b, op, get_case_fn):
         bf = Float32.from_bits(b)
         z = op(af, bf)
         expected_responses.append((z.get_bits(), mid))
-        #print (af, bf, z)
         actual = yield from get_case_fn(dut, a, b, mid)
         actual_responses.append(actual)