more code-shuffle

[ieee754fpu.git] / src / ieee754 / add / concurrentunit.py

diff --git a/src/ieee754/add/concurrentunit.py b/src/ieee754/add/concurrentunit.py
index dbe4a964ef4cea1772a23c661f8313754b026cab..82b81ff5d315e5bdb586a560f4eaa61420aa923f 100644 (file)
--- a/src/ieee754/add/concurrentunit.py
+++ b/src/ieee754/add/concurrentunit.py
@@ -6,16 +6,9 @@ from math import log
 from nmigen import Module
 from nmigen.cli import main, verilog
 
-from singlepipe import PassThroughStage
-from multipipe import CombMuxOutPipe
-from multipipe import PriorityCombMuxInPipe
-
-from ieee754.fpcommon.getop import FPADDBaseData
-from ieee754.fpcommon.denorm import FPSCData
-from ieee754.fpcommon.pack import FPPackData
-from ieee754.fpcommon.normtopack import FPNormToPack
-from ieee754.fpadd.specialcases import FPAddSpecialCasesDeNorm
-from ieee754.fpadd.addstages import FPAddAlignSingleAdd
+from nmutil.singlepipe import PassThroughStage
+from nmutil.multipipe import CombMuxOutPipe
+from nmutil.multipipe import PriorityCombMuxInPipe
 
 
 def num_bits(n):