reorganise imports

[ieee754fpu.git] / src / ieee754 / add / nmigen_add_experiment.py

diff --git a/src/ieee754/add/nmigen_add_experiment.py b/src/ieee754/add/nmigen_add_experiment.py
index ecb1d35b14350f67e95f51522dc7407b2f056bc8..773e3aee155d6f0d90ed42e99a97f13ae8a14e36 100644 (file)
--- a/src/ieee754/add/nmigen_add_experiment.py
+++ b/src/ieee754/add/nmigen_add_experiment.py
@@ -3,8 +3,8 @@
 # 2013-12-12
 
 from nmigen.cli import main, verilog
-from fpadd.statemachine import FPADDBase, FPADD
-from fpadd.pipeline import FPADDMuxInOut
+from ieee754.fpadd.statemachine import FPADDBase, FPADD
+from ieee754.fpadd.pipeline import FPADDMuxInOut
 
 if __name__ == "__main__":
     if True: