relative imports

[ieee754fpu.git] / src / ieee754 / add / test_fsm_experiment.py

diff --git a/src/ieee754/add/test_fsm_experiment.py b/src/ieee754/add/test_fsm_experiment.py
index 17cee24ebb4cb5e85cd49311140017912f4488df..eeff6f0aae714be8b2f125b41f69bcab1608e442 100644 (file)
--- a/src/ieee754/add/test_fsm_experiment.py
+++ b/src/ieee754/add/test_fsm_experiment.py
@@ -6,11 +6,11 @@ from nmigen import Module, Signal, Const, Cat, Elaboratable
 from nmigen.cli import main, verilog, rtlil
 from nmigen.compat.sim import run_simulation
 
-
-from fpbase import FPNumIn, FPNumOut, FPOpIn, FPOpOut, FPBase, FPState
-from nmoperator import eq
-from singlepipe import SimpleHandshake, ControlBase
-from test_buf_pipe import data_chain2, Test5
+from ieee754.fpcommon.fpbase import (FPNumIn, FPNumOut, FPOpIn,
+                                     FPOpOut, FPBase)
+from nmutil.nmoperator import eq
+from nmutil.singlepipe import SimpleHandshake, ControlBase
+from nmutil.test.test_buf_pipe import data_chain2, Test5
 
 
 class FPDIV(FPBase, Elaboratable):