add ignore on *.v and *.il

[ieee754fpu.git] / src / ieee754 / add / test_inout_mux_pipe.py

diff --git a/src/ieee754/add/test_inout_mux_pipe.py b/src/ieee754/add/test_inout_mux_pipe.py
index 35abe2eaf46b3aa148826b6821640cf39dfe2786..221ece1db7f4b51ab7269f08c915b2ebba363fa1 100644 (file)
--- a/src/ieee754/add/test_inout_mux_pipe.py
+++ b/src/ieee754/add/test_inout_mux_pipe.py
@@ -11,9 +11,9 @@ from nmigen import Module, Signal, Cat, Value, Elaboratable
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from multipipe import CombMultiOutPipeline, CombMuxOutPipe
-from multipipe import PriorityCombMuxInPipe
-from singlepipe import SimpleHandshake, RecordObject, Object
+from nmutil.multipipe import CombMultiOutPipeline, CombMuxOutPipe
+from nmutil.multipipe import PriorityCombMuxInPipe
+from nmutil.singlepipe import SimpleHandshake, RecordObject, Object
 
 
 class PassData2(RecordObject):