add ignore on *.v and *.il

[ieee754fpu.git] / src / ieee754 / add / test_outmux_pipe.py

diff --git a/src/ieee754/add/test_outmux_pipe.py b/src/ieee754/add/test_outmux_pipe.py
index b674a87069f82394ad771a5f658d8ee0838721e5..768d9d9a09e6efb1e76c2217e27d2e5192c8778e 100644 (file)
--- a/src/ieee754/add/test_outmux_pipe.py
+++ b/src/ieee754/add/test_outmux_pipe.py
@@ -4,8 +4,8 @@ from nmigen import Module, Signal, Cat, Elaboratable
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from multipipe import CombMuxOutPipe
-from singlepipe import SimpleHandshake, PassThroughHandshake, RecordObject
+from nmutil.multipipe import CombMuxOutPipe
+from nmutil.singlepipe import SimpleHandshake, PassThroughHandshake, RecordObject
 
 
 class PassInData(RecordObject):