more code-shuffle

[ieee754fpu.git] / src / ieee754 / fpadd / add0.py

diff --git a/src/ieee754/fpadd/add0.py b/src/ieee754/fpadd/add0.py
index 76790fe22bbd4d48220e98b78d694b8ef2567180..db04506cfb35335176cf4ef6a66dbc945a083ffb 100644 (file)
--- a/src/ieee754/fpadd/add0.py
+++ b/src/ieee754/fpadd/add0.py
@@ -5,9 +5,9 @@
 from nmigen import Module, Signal, Cat, Elaboratable
 from nmigen.cli import main, verilog
 
-from fpbase import FPNumBase
-from fpbase import FPState
-from fpcommon.denorm import FPSCData
+from ieee754.fpcommon.fpbase import FPNumBase
+from ieee754.fpcommon.fpbase import FPState
+from ieee754.fpcommon.denorm import FPSCData
 
 
 class FPAddStage0Data: