more code-shuffle

[ieee754fpu.git] / src / ieee754 / fpadd / add1.py

diff --git a/src/ieee754/fpadd/add1.py b/src/ieee754/fpadd/add1.py
index 1c0ff27a3d7e149ec30c9d121b3c05fe6e130073..1205431272f76e74b21bf4a440924abcac8fb05d 100644 (file)
--- a/src/ieee754/fpadd/add1.py
+++ b/src/ieee754/fpadd/add1.py
@@ -6,7 +6,7 @@ from nmigen import Module, Signal, Elaboratable
 from nmigen.cli import main, verilog
 from math import log
 
-from fpbase import FPState
+from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.postcalc import FPAddStage1Data
 from .add0 import FPAddStage0Data