reorganise imports

[ieee754fpu.git] / src / ieee754 / fpadd / add1.py

diff --git a/src/ieee754/fpadd/add1.py b/src/ieee754/fpadd/add1.py
index 679f5176d2d9227c41637d9fb9db2d6c08c6845d..1c0ff27a3d7e149ec30c9d121b3c05fe6e130073 100644 (file)
--- a/src/ieee754/fpadd/add1.py
+++ b/src/ieee754/fpadd/add1.py
@@ -7,8 +7,8 @@ from nmigen.cli import main, verilog
 from math import log
 
 from fpbase import FPState
-from fpcommon.postcalc import FPAddStage1Data
-from fpadd.add0 import FPAddStage0Data
+from ieee754.fpcommon.postcalc import FPAddStage1Data
+from .add0 import FPAddStage0Data
 
 
 class FPAddStage1Mod(FPState, Elaboratable):