more code-shuffle

[ieee754fpu.git] / src / ieee754 / fpadd / addstages.py

diff --git a/src/ieee754/fpadd/addstages.py b/src/ieee754/fpadd/addstages.py
index f5703aeceaacd6c99855b9977aab4d95a8432b62..b398a2742072246d3f0dc523804c5b09517fc556 100644 (file)
--- a/src/ieee754/fpadd/addstages.py
+++ b/src/ieee754/fpadd/addstages.py
@@ -5,15 +5,15 @@
 from nmigen import Module
 from nmigen.cli import main, verilog
 
-from singlepipe import (StageChain, SimpleHandshake,
+from nmutil.singlepipe import (StageChain, SimpleHandshake,
                         PassThroughStage)
 
-from fpbase import FPState
-from fpcommon.denorm import FPSCData
-from fpcommon.postcalc import FPAddStage1Data
-from fpadd.align import FPAddAlignSingleMod
-from fpadd.add0 import FPAddStage0Mod
-from fpadd.add1 import FPAddStage1Mod
+from ieee754.fpcommon.fpbase import FPState
+from ieee754.fpcommon.denorm import FPSCData
+from ieee754.fpcommon.postcalc import FPAddStage1Data
+from .align import FPAddAlignSingleMod
+from .add0 import FPAddStage0Mod
+from .add1 import FPAddStage1Mod
 
 
 class FPAddAlignSingleAdd(FPState, SimpleHandshake):