resolve awful meta-class hacking (with thanks to jsbueno on stackexchange)

[ieee754fpu.git] / src / ieee754 / fpadd / addstages.py

diff --git a/src/ieee754/fpadd/addstages.py b/src/ieee754/fpadd/addstages.py
index 2bc23df0dabf89f8a4e194d5e573a88d5d740d0e..f875ef920247243e9bfd3265055c66cd87584e1c 100644 (file)
--- a/src/ieee754/fpadd/addstages.py
+++ b/src/ieee754/fpadd/addstages.py
@@ -5,8 +5,8 @@
 from nmigen import Module
 from nmigen.cli import main, verilog
 
-from nmutil.singlepipe import (StageChain, SimpleHandshake,
-                        PassThroughStage)
+from nmutil.singlepipe import StageChain
+from ieee754.pipeline import DynamicPipe
 
 from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.denorm import FPSCData
@@ -15,13 +15,12 @@ from ieee754.fpadd.align import FPAddAlignSingleMod
 from ieee754.fpadd.add0 import FPAddStage0Mod
 from ieee754.fpadd.add1 import FPAddStage1Mod
 
-
-class FPAddAlignSingleAdd(FPState, SimpleHandshake):
+class FPAddAlignSingleAdd(DynamicPipe):
 
     def __init__(self, pspec):
-        FPState.__init__(self, "align")
+        #FPState.__init__(self, "align")
         self.pspec = pspec
-        SimpleHandshake.__init__(self, self) # pipeline is its own stage
+        super().__init__(pspec)
         self.a1o = self.ospec()
 
     def ispec(self):