get test_add working after reorg

[ieee754fpu.git] / src / ieee754 / fpadd / pipeline.py

diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py
index 5c4eed18d9aba94a9956c425e216e1ba579192dd..7b37a6877d797ee2b0a0d4f03556ec3c151e4981 100644 (file)
--- a/src/ieee754/fpadd/pipeline.py
+++ b/src/ieee754/fpadd/pipeline.py
@@ -5,9 +5,10 @@
 from nmigen import Module
 from nmigen.cli import main, verilog
 
-from singlepipe import (ControlBase, SimpleHandshake, PassThroughStage)
-from multipipe import CombMuxOutPipe
-from multipipe import PriorityCombMuxInPipe
+from nmutil.singlepipe import (ControlBase, SimpleHandshake, PassThroughStage)
+from nmutil.multipipe import CombMuxOutPipe
+from nmutil.multipipe import PriorityCombMuxInPipe
+from nmutil.concurrentunit import ReservationStations, num_bits
 
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.denorm import FPSCData
@@ -16,7 +17,6 @@ from ieee754.fpcommon.normtopack import FPNormToPack
 from .specialcases import FPAddSpecialCasesDeNorm
 from .addstages import FPAddAlignSingleAdd
 
-from concurrentunit import ReservationStations, num_bits
 
 
 class FPADDBasePipe(ControlBase):