debug fpmul pipeline

[ieee754fpu.git] / src / ieee754 / fpmul / specialcases.py

diff --git a/src/ieee754/fpmul/specialcases.py b/src/ieee754/fpmul/specialcases.py
index fec43fabeae7351a224528d6848f3ad32e0827f6..92dd75afc17a1869d551d8dd97753ce66397f02e 100644 (file)
--- a/src/ieee754/fpmul/specialcases.py
+++ b/src/ieee754/fpmul/specialcases.py
@@ -73,6 +73,9 @@ class FPMulSpecialCasesMod:
         sabx = Signal(reset_less=True)   # sign a xor b (sabx, get it?)
         m.d.comb += sabx.eq(a1.s ^ b1.s)
 
+        abnan = Signal(reset_less=True)
+        m.d.comb += abnan.eq(a1.is_nan | b1.is_nan)
+
         # if a is NaN or b is NaN return NaN
         with m.If(abnan):
             m.d.comb += self.o.out_do_z.eq(1)