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[ieee754fpu.git] / src / ieee754 / fpmul / test / test_mul.py

diff --git a/src/ieee754/fpmul/test/test_mul.py b/src/ieee754/fpmul/test/test_mul.py
index 4f879ee1cc33a3f511082883517255d1b690be43..f58a9f66b053d576d2a7da5a1944aa2cf8aa1ff1 100644 (file)
--- a/src/ieee754/fpmul/test/test_mul.py
+++ b/src/ieee754/fpmul/test/test_mul.py
@@ -8,7 +8,8 @@ from nmigen.compat.sim import run_simulation
 
 from ieee754.fpmul.fmul import FPMUL
 
-from ieee754.fpcommon.test.unit_test_single import (get_mantissa, get_exponent, get_sign, is_nan,
+from ieee754.fpcommon.test.unit_test_single import (get_mantissa, get_exponent,
+                                get_sign, is_nan,
                                 is_inf, is_pos_inf, is_neg_inf,
                                 match, get_case, check_case, run_fpunit,
                                 run_edge_cases, run_corner_cases)