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dependency matrix (Reg to FU)
[ieee754fpu.git]
/
src
/
scoreboard
/
dependence_cell.py
diff --git
a/src/scoreboard/dependence_cell.py
b/src/scoreboard/dependence_cell.py
index 1c8a0095967e51f4e9dda213617d4413b67c4cb9..7c2d883dbcb53f36e7b0168cde7fdc7b965c6112 100644
(file)
--- a/
src/scoreboard/dependence_cell.py
+++ b/
src/scoreboard/dependence_cell.py
@@
-3,6
+3,7
@@
from nmigen.cli import verilog, rtlil
from nmigen import Module, Signal, Elaboratable
from nmutil.latch import SRLatch
from nmigen import Module, Signal, Elaboratable
from nmutil.latch import SRLatch
+
class DependenceCell(Elaboratable):
""" implements 11.4.7 mitch alsup dependence cell, p27
"""
class DependenceCell(Elaboratable):
""" implements 11.4.7 mitch alsup dependence cell, p27
"""
@@
-73,6
+74,7
@@
class DependenceCell(Elaboratable):
def ports(self):
return list(self)
def ports(self):
return list(self)
+
def dcell_sim(dut):
yield dut.dest_i.eq(1)
yield dut.issue_i.eq(1)
def dcell_sim(dut):
yield dut.dest_i.eq(1)
yield dut.issue_i.eq(1)