dependency matrix (Reg to FU)

[ieee754fpu.git] / src / scoreboard / dependence_cell.py

diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py
index 3624d1a48d1da1c6dd850c769260f97d5ee8ed68..7c2d883dbcb53f36e7b0168cde7fdc7b965c6112 100644 (file)
--- a/src/scoreboard/dependence_cell.py
+++ b/src/scoreboard/dependence_cell.py
@@ -3,6 +3,7 @@ from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Elaboratable
 from nmutil.latch import SRLatch
 
+
 class DependenceCell(Elaboratable):
     """ implements 11.4.7 mitch alsup dependence cell, p27
     """
@@ -45,15 +46,15 @@ class DependenceCell(Elaboratable):
         m.d.sync += src2_l.r.eq(self.go_read_i)
 
         # FU "Forward Progress" (read out horizontally)
-        m.d.comb += self.dest_rsel_o.eq(dest_l.qn & self.go_write_i)
-        m.d.comb += self.src1_rsel_o.eq(src1_l.qn & self.go_read_i)
-        m.d.comb += self.src2_rsel_o.eq(src2_l.qn & self.go_read_i)
-
-        # Register File Select (read out vertically)
         m.d.comb += self.dest_fwd_o.eq(dest_l.qn & self.dest_i)
         m.d.comb += self.src1_fwd_o.eq(src1_l.qn & self.src1_i)
         m.d.comb += self.src2_fwd_o.eq(src2_l.qn & self.src2_i)
 
+        # Register File Select (read out vertically)
+        m.d.comb += self.dest_rsel_o.eq(dest_l.qn & self.go_write_i)
+        m.d.comb += self.src1_rsel_o.eq(src1_l.qn & self.go_read_i)
+        m.d.comb += self.src2_rsel_o.eq(src2_l.qn & self.go_read_i)
+
         return m
 
     def __iter__(self):
@@ -73,6 +74,7 @@ class DependenceCell(Elaboratable):
     def ports(self):
         return list(self)
 
+
 def dcell_sim(dut):
     yield dut.dest_i.eq(1)
     yield dut.issue_i.eq(1)