corrections to ld-st cell and sparse-matrix

[ieee754fpu.git] / src / scoreboard / ldst_dep_cell.py

diff --git a/src/scoreboard/ldst_dep_cell.py b/src/scoreboard/ldst_dep_cell.py
index f1264bd288e3558cda3eaae0c8a370abcffbaa51..40e1ffbc4d8d724961ec46da29569e12ae64ce85 100644 (file)
--- a/src/scoreboard/ldst_dep_cell.py
+++ b/src/scoreboard/ldst_dep_cell.py
@@ -1,3 +1,10 @@
+""" Mitch Alsup 6600-style LD/ST scoreboard Dependency Cell
+
+Relevant bugreports:
+* http://bugs.libre-riscv.org/show_bug.cgi?id=81
+
+"""
+
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Elaboratable
@@ -6,10 +13,6 @@ from nmutil.latch import SRLatch
 
 class LDSTDepCell(Elaboratable):
     """ implements 11.4.12 mitch alsup load/store dependence cell, p45
-
-        note: the load-hold-store / store-hold-load both come through from
-        the previous cell and accumulate using ORing to create priority
-        picking (in the sparse-matrix, which is where the cells are wired up)
     """
     def __init__(self):
         # inputs
@@ -19,8 +22,6 @@ class LDSTDepCell(Elaboratable):
 
         self.load_hit_i = Signal(reset_less=True) # load hit in (right)
         self.stwd_hit_i = Signal(reset_less=True) # store w/ data hit in (right)
-        self.ld_hold_st_i = Signal(reset_less=True) # load holds st in (right)
-        self.st_hold_ld_i = Signal(reset_less=True) # st holds load in (right)
 
         # outputs (latched rd/wr pend)
         self.ld_hold_st_o = Signal(reset_less=True) # load holds st out (left)
@@ -28,8 +29,8 @@ class LDSTDepCell(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.war_l = war_l = SRLatch() # Write After Read Latch
-        m.submodules.raw_l = raw_l = SRLatch() # Read After Write Latch
+        m.submodules.war_l = war_l = SRLatch(sync=False) # WriteAfterRead Latch
+        m.submodules.raw_l = raw_l = SRLatch(sync=False) # ReadAfterWrite Latch
 
         # issue & store & load - used for both WAR and RAW Setting
         i_s_l = Signal(reset_less=True)
@@ -44,10 +45,8 @@ class LDSTDepCell(Elaboratable):
         m.d.comb += raw_l.r.eq(self.stor_i) # reset on ST
 
         # Hold results (read out horizontally, accumulate in OR fashion)
-        lhs = war_l.qn & self.load_hit_i
-        shl = raw_l.qn & self.stwd_hit_i
-        m.d.comb += self.ld_hold_st_o.eq(self.ld_hold_st_i | lhs)
-        m.d.comb += self.st_hold_ld_o.eq(self.st_hold_ld_i | shl)
+        m.d.comb += self.ld_hold_st_o.eq(war_l.qn & self.load_hit_i)
+        m.d.comb += self.st_hold_ld_o.eq(raw_l.qn & self.stwd_hit_i)
 
         return m
 
@@ -57,8 +56,6 @@ class LDSTDepCell(Elaboratable):
         yield self.issue_i
         yield self.load_hit_i
         yield self.stwd_hit_i
-        yield self.ld_hold_st_i
-        yield self.st_hold_ld_i
         yield self.ld_hold_st_o
         yield self.st_hold_ld_o