add comments

[ieee754fpu.git] / src / scoreboard / ldst_matrix.py

diff --git a/src/scoreboard/ldst_matrix.py b/src/scoreboard/ldst_matrix.py
index 563490f174b26b453341f1128ef329a76bba442f..07a832d63c75b477d86794d332d322f05502086a 100644 (file)
--- a/src/scoreboard/ldst_matrix.py
+++ b/src/scoreboard/ldst_matrix.py
@@ -1,15 +1,27 @@
+""" Mitch Alsup 6600-style LD/ST Memory Scoreboard Matrix (sparse vector)
+
+6600 LD/ST Dependency Table Matrix inputs / outputs
+---------------------------------------------------
+
+Relevant comments (p45-46):
+
+* If there are no WAR dependencies on a Load instruction with a computed
+  address it can assert Bank_Addressable and Translate_Addressable.
+
+* If there are no RAW dependencies on a Store instruction with both a
+  write permission and store data present it can assert Bank_Addressable
+
+Relevant bugreports:
+* http://bugs.libre-riscv.org/show_bug.cgi?id=81
+
+"""
+
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Elaboratable, Array, Cat, Const
 
 from ldst_dep_cell import LDSTDepCell
 
-"""
-
- 6600 LD/ST Dependency Table Matrix inputs / outputs
- ---------------------------------------------------
-
-"""
 
 class LDSTDepMatrix(Elaboratable):
     """ implements 11.4.12 mitch alsup LD/ST Dependency Matrix, p46