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[ieee754fpu.git] / src / scoreboard / ldst_matrix.py

diff --git a/src/scoreboard/ldst_matrix.py b/src/scoreboard/ldst_matrix.py
index daeb14274ecd478e6ba601885f2445535eae0e70..07a832d63c75b477d86794d332d322f05502086a 100644 (file)
--- a/src/scoreboard/ldst_matrix.py
+++ b/src/scoreboard/ldst_matrix.py
@@ -1,15 +1,27 @@
+""" Mitch Alsup 6600-style LD/ST Memory Scoreboard Matrix (sparse vector)
+
+6600 LD/ST Dependency Table Matrix inputs / outputs
+---------------------------------------------------
+
+Relevant comments (p45-46):
+
+* If there are no WAR dependencies on a Load instruction with a computed
+  address it can assert Bank_Addressable and Translate_Addressable.
+
+* If there are no RAW dependencies on a Store instruction with both a
+  write permission and store data present it can assert Bank_Addressable
+
+Relevant bugreports:
+* http://bugs.libre-riscv.org/show_bug.cgi?id=81
+
+"""
+
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Elaboratable, Array, Cat, Const
 
 from ldst_dep_cell import LDSTDepCell
 
-"""
-
- 6600 LD/ST Dependency Table Matrix inputs / outputs
- ---------------------------------------------------
-
-"""
 
 class LDSTDepMatrix(Elaboratable):
     """ implements 11.4.12 mitch alsup LD/ST Dependency Matrix, p46
@@ -56,14 +68,12 @@ class LDSTDepMatrix(Elaboratable):
         sh_l = []
         for fu in range(self.n_ldst):
             dc = dm[fu]
-            # OR the load-hold-store / store-hold-load cell outputs in...
-            _lhs = lhs
-            _shl = shl
-            lhs = Signal(reset_less=True)
-            shl = Signal(reset_less=True)
-            m.d.comb += [lhs.eq(_lhs | dc.ld_hold_st_o),
-                         shl.eq(_shl | dc.st_hold_ld_o)
+            # connect up the load/hold/store cell in/out (starts as a const)
+            m.d.comb += [dc.ld_hold_st_i.eq(lhs),
+                         dc.st_hold_ld_i.eq(shl)
                         ]
+            lhs = dc.ld_hold_st_o
+            shl = dc.st_hold_ld_o
             # accumulate load-hold-store / store-hold-load bits
             lhs_l.append(lhs)
             shl_l.append(shl)
@@ -88,7 +98,7 @@ class LDSTDepMatrix(Elaboratable):
         return m
 
     def __iter__(self):
-        yield self.load_i  
+        yield self.load_i
         yield self.stor_i
         yield self.issue_i
         yield self.load_hit_i