add function unit read/write pending

[ieee754fpu.git] / src / scoreboard / reg_select.py

diff --git a/src/scoreboard/reg_select.py b/src/scoreboard/reg_select.py
index 9d16741b61e156cd030e125d3627ea7139c13222..04deaac549c4f62d3673363c4e4117b946751b21 100644 (file)
--- a/src/scoreboard/reg_select.py
+++ b/src/scoreboard/reg_select.py
@@ -1,4 +1,5 @@
-from nmigen import Elaboratable, Module, Array, Signal
+from nmigen import Elaboratable, Module, Signal
+
 
 class RegReservation(Elaboratable):
     def __init__(self, fu_count):