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dependency matrix (Reg to FU)
[ieee754fpu.git]
/
src
/
scoreboard
/
reg_select.py
diff --git
a/src/scoreboard/reg_select.py
b/src/scoreboard/reg_select.py
index 04deaac549c4f62d3673363c4e4117b946751b21..eca3328e267b2cc7d2050a68700a22aa77a77347 100644
(file)
--- a/
src/scoreboard/reg_select.py
+++ b/
src/scoreboard/reg_select.py
@@
-1,7
+1,10
@@
from nmigen import Elaboratable, Module, Signal
from nmigen import Elaboratable, Module, Signal
-class RegReservation(Elaboratable):
+class Reg_Rsv(Elaboratable):
+ """ these are allocated per-Register (vertically),
+ and are each of length fu_count
+ """
def __init__(self, fu_count):
self.fu_count = fu_count
self.dest_rsel_i = Signal(fu_count, reset_less=True)
def __init__(self, fu_count):
self.fu_count = fu_count
self.dest_rsel_i = Signal(fu_count, reset_less=True)
@@
-11,7
+14,7
@@
class RegReservation(Elaboratable):
self.src1_rsel_o = Signal(reset_less=True)
self.src2_rsel_o = Signal(reset_less=True)
self.src1_rsel_o = Signal(reset_less=True)
self.src2_rsel_o = Signal(reset_less=True)
- def elaborat
abl
e(self, platform):
+ def elaborate(self, platform):
m = Module()
m.d.comb += self.dest_rsel_o.eq(self.dest_rsel_i.bool())
m.d.comb += self.src1_rsel_o.eq(self.src1_rsel_i.bool())
m = Module()
m.d.comb += self.dest_rsel_o.eq(self.dest_rsel_i.bool())
m.d.comb += self.src1_rsel_o.eq(self.src1_rsel_i.bool())