X-Git-Url: https://git.libre-soc.org/?p=ieee754fpu.git;a=blobdiff_plain;f=src%2Fieee754%2Ffpadd%2Fpipeline.py;h=7b37a6877d797ee2b0a0d4f03556ec3c151e4981;hp=eea893552047d772f8ba7adf930db3a6e729e118;hb=b2672aebd8aac9aac3a2769b9a0ce509e86b0da6;hpb=f09f35af37956dc1e3cc01aadc84ad07a711d2d4

diff --git a/src/ieee754/fpadd/pipeline.py b/src/ieee754/fpadd/pipeline.py
index eea89355..7b37a687 100644
--- a/src/ieee754/fpadd/pipeline.py
+++ b/src/ieee754/fpadd/pipeline.py
@@ -8,6 +8,7 @@ from nmigen.cli import main, verilog
 from nmutil.singlepipe import (ControlBase, SimpleHandshake, PassThroughStage)
 from nmutil.multipipe import CombMuxOutPipe
 from nmutil.multipipe import PriorityCombMuxInPipe
+from nmutil.concurrentunit import ReservationStations, num_bits
 
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.denorm import FPSCData
@@ -16,7 +17,6 @@ from ieee754.fpcommon.normtopack import FPNormToPack
 from .specialcases import FPAddSpecialCasesDeNorm
 from .addstages import FPAddAlignSingleAdd
 
-from concurrentunit import ReservationStations, num_bits
 
 
 class FPADDBasePipe(ControlBase):