X-Git-Url: https://git.libre-soc.org/?p=ieee754fpu.git;a=blobdiff_plain;f=src%2Fscoreboard%2Fdependence_cell.py;h=7c2d883dbcb53f36e7b0168cde7fdc7b965c6112;hp=1c8a0095967e51f4e9dda213617d4413b67c4cb9;hb=54a5801833ba8df5c5895e0cd4cd0264942933ed;hpb=43c4c718784864113e97c08925524359fe52af4b

diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py
index 1c8a0095..7c2d883d 100644
--- a/src/scoreboard/dependence_cell.py
+++ b/src/scoreboard/dependence_cell.py
@@ -3,6 +3,7 @@ from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Elaboratable
 from nmutil.latch import SRLatch
 
+
 class DependenceCell(Elaboratable):
     """ implements 11.4.7 mitch alsup dependence cell, p27
     """
@@ -73,6 +74,7 @@ class DependenceCell(Elaboratable):
     def ports(self):
         return list(self)
 
+
 def dcell_sim(dut):
     yield dut.dest_i.eq(1)
     yield dut.issue_i.eq(1)