X-Git-Url: https://git.libre-soc.org/?p=ieee754fpu.git;a=blobdiff_plain;f=src%2Fscoreboard%2Ffu_wr_pending.py;h=9b177ff041db5b470f8c2fba9ad0f9242fd7bb90;hp=9bba20e24e6a375e4803a2c62b80955428e1552d;hb=54a5801833ba8df5c5895e0cd4cd0264942933ed;hpb=43c4c718784864113e97c08925524359fe52af4b

diff --git a/src/scoreboard/fu_wr_pending.py b/src/scoreboard/fu_wr_pending.py
index 9bba20e2..9b177ff0 100644
--- a/src/scoreboard/fu_wr_pending.py
+++ b/src/scoreboard/fu_wr_pending.py
@@ -1,20 +1,23 @@
-from nmigen import Elaboratable, Module, Signal
+from nmigen import Elaboratable, Module, Signal, Cat
 
 
-class FUReadWritePending(Elaboratable):
+class FU_RW_Pend(Elaboratable):
+    """ these are allocated per-FU (horizontally),
+        and are of length reg_count
+    """
     def __init__(self, reg_count):
         self.reg_count = reg_count
-        self.dest_fwd_i = Signal(fu_count, reset_less=True)
-        self.src1_fwd_i = Signal(fu_count, reset_less=True)
-        self.src2_fwd_i = Signal(fu_count, reset_less=True)
+        self.dest_fwd_i = Signal(reg_count, reset_less=True)
+        self.src1_fwd_i = Signal(reg_count, reset_less=True)
+        self.src2_fwd_i = Signal(reg_count, reset_less=True)
 
-        self.wr_pend_o = Signal(reset_less=True)
-        self.rd_pend_o = Signal(reset_less=True)
+        self.reg_wr_pend_o = Signal(reset_less=True)
+        self.reg_rd_pend_o = Signal(reset_less=True)
 
-    def elaboratable(self, platform):
+    def elaborate(self, platform):
         m = Module()
         srces = Cat(self.src1_fwd_i, self.src2_fwd_i)
-        m.d.comb += self.wr_pend_o.eq(self.dest_fwd_i.bool())
-        m.d.comb += self.rd_pend_o.eq(srces.bool() 
+        m.d.comb += self.reg_wr_pend_o.eq(self.dest_fwd_i.bool())
+        m.d.comb += self.reg_rd_pend_o.eq(srces.bool())
         return m