X-Git-Url: https://git.libre-soc.org/?p=ieee754fpu.git;a=blobdiff_plain;f=src%2Fscoreboard%2Freg_select.py;h=eca3328e267b2cc7d2050a68700a22aa77a77347;hp=04deaac549c4f62d3673363c4e4117b946751b21;hb=54a5801833ba8df5c5895e0cd4cd0264942933ed;hpb=43c4c718784864113e97c08925524359fe52af4b

diff --git a/src/scoreboard/reg_select.py b/src/scoreboard/reg_select.py
index 04deaac5..eca3328e 100644
--- a/src/scoreboard/reg_select.py
+++ b/src/scoreboard/reg_select.py
@@ -1,7 +1,10 @@
 from nmigen import Elaboratable, Module, Signal
 
 
-class RegReservation(Elaboratable):
+class Reg_Rsv(Elaboratable):
+    """ these are allocated per-Register (vertically),
+        and are each of length fu_count
+    """
     def __init__(self, fu_count):
         self.fu_count = fu_count
         self.dest_rsel_i = Signal(fu_count, reset_less=True)
@@ -11,7 +14,7 @@ class RegReservation(Elaboratable):
         self.src1_rsel_o = Signal(reset_less=True)
         self.src2_rsel_o = Signal(reset_less=True)
 
-    def elaboratable(self, platform):
+    def elaborate(self, platform):
         m = Module()
         m.d.comb += self.dest_rsel_o.eq(self.dest_rsel_i.bool())
         m.d.comb += self.src1_rsel_o.eq(self.src1_rsel_i.bool())