From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 2 May 2019 23:26:31 +0000 (+0100)
Subject: get inout mux test running on nose3
X-Git-Tag: ls180-24jan2020~1057
X-Git-Url: https://git.libre-soc.org/?p=ieee754fpu.git;a=commitdiff_plain;h=e222459dc6f248b984cdf96f619f271e5cd26de7

get inout mux test running on nose3
---

diff --git a/src/nmutil/test/test_inout_mux_pipe.py b/src/nmutil/test/test_inout_mux_pipe.py
index 221ece1d..fe743551 100644
--- a/src/nmutil/test/test_inout_mux_pipe.py
+++ b/src/nmutil/test/test_inout_mux_pipe.py
@@ -65,7 +65,7 @@ class InputTest:
     def send(self, mid):
         for i in range(self.tlen):
             op2 = self.di[mid][i]
-            rs = dut.p[mid]
+            rs = self.dut.p[mid]
             yield rs.valid_i.eq(1)
             yield rs.data_i.data.eq(op2)
             yield rs.data_i.idx.eq(i)
@@ -212,7 +212,7 @@ class TestInOutPipe(Elaboratable):
         return self._ports
 
 
-if __name__ == '__main__':
+def test1():
     dut = TestInOutPipe()
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_inoutmux_pipe.il", "w") as f:
@@ -227,3 +227,5 @@ if __name__ == '__main__':
                         ],
                    vcd_name="test_inoutmux_pipe.vcd")
 
+if __name__ == '__main__':
+    test1()