ieee754fpu.git
5 years agoconnect normalisation directly to round with combinatorial logic
Luke Kenneth Casson Leighton [Sat, 9 Mar 2019 09:24:50 +0000 (09:24 +0000)]
connect normalisation directly to round with combinatorial logic

5 years agobig reorganisation
Luke Kenneth Casson Leighton [Sat, 9 Mar 2019 09:13:47 +0000 (09:13 +0000)]
big reorganisation

splitting out Normalisation Single/Multi
adding beginnings of combinatorial-chained normalisation thru pack

5 years agosplit out into 2 functions, longer and compact fragment
Luke Kenneth Casson Leighton [Sat, 9 Mar 2019 07:25:28 +0000 (07:25 +0000)]
split out into 2 functions, longer and compact fragment

5 years agomove in_t_ack into FPGet2Op setup
Luke Kenneth Casson Leighton [Sat, 9 Mar 2019 07:18:47 +0000 (07:18 +0000)]
move in_t_ack into FPGet2Op setup

5 years agoadd "compact" option
Luke Kenneth Casson Leighton [Sat, 9 Mar 2019 07:18:01 +0000 (07:18 +0000)]
add "compact" option

5 years agomain on FPADD not on FPADDBase
Luke Kenneth Casson Leighton [Fri, 8 Mar 2019 12:59:11 +0000 (12:59 +0000)]
main on FPADD not on FPADDBase

5 years agobig reorg, got FPADD to work using new FPADDBase
Luke Kenneth Casson Leighton [Fri, 8 Mar 2019 12:53:15 +0000 (12:53 +0000)]
big reorg, got FPADD to work using new FPADDBase

5 years agoadd some comments to FPAddBase
Luke Kenneth Casson Leighton [Wed, 6 Mar 2019 21:46:01 +0000 (21:46 +0000)]
add some comments to FPAddBase

5 years agoin the middle of rewiring FPADD to use FPADDBase
Luke Kenneth Casson Leighton [Wed, 6 Mar 2019 12:14:47 +0000 (12:14 +0000)]
in the middle of rewiring FPADD to use FPADDBase

5 years agosplit out main stages of add to separate class, FPADDBase
Luke Kenneth Casson Leighton [Wed, 6 Mar 2019 06:09:15 +0000 (06:09 +0000)]
split out main stages of add to separate class, FPADDBase

5 years agoadd function unit module
Luke Kenneth Casson Leighton [Wed, 6 Mar 2019 06:08:20 +0000 (06:08 +0000)]
add function unit module

5 years agocorrect syntax error
Luke Kenneth Casson Leighton [Wed, 6 Mar 2019 06:08:09 +0000 (06:08 +0000)]
correct syntax error

5 years agoadd reservation station row module
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 03:06:04 +0000 (03:06 +0000)]
add reservation station row module

5 years agoadd MID testing
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:50:36 +0000 (02:50 +0000)]
add MID testing

5 years agoadd id to pack and putz
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:36:50 +0000 (02:36 +0000)]
add id to pack and putz

5 years agoadd id to FPPack
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:33:16 +0000 (02:33 +0000)]
add id to FPPack

5 years agoadd id to FPCorrections
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:30:20 +0000 (02:30 +0000)]
add id to FPCorrections

5 years agoadd id to FPRound
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:28:48 +0000 (02:28 +0000)]
add id to FPRound

5 years agoadd id to norm1
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:26:13 +0000 (02:26 +0000)]
add id to norm1

5 years agoadd id to stage1
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:24:54 +0000 (02:24 +0000)]
add id to stage1

5 years agoadd id to stage0
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:22:19 +0000 (02:22 +0000)]
add id to stage0

5 years agoadd id to align
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:18:39 +0000 (02:18 +0000)]
add id to align

5 years agoadd id to denorm
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 02:15:21 +0000 (02:15 +0000)]
add id to denorm

5 years agoadd id passthrough to specialcases class
Luke Kenneth Casson Leighton [Tue, 5 Mar 2019 00:58:31 +0000 (00:58 +0000)]
add id passthrough to specialcases class

5 years agoreorg special cases setup
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 23:41:18 +0000 (23:41 +0000)]
reorg special cases setup

5 years agoadd id_width to parameters
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 23:38:19 +0000 (23:38 +0000)]
add id_width to parameters

5 years agoremove unneeded code
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 10:59:07 +0000 (10:59 +0000)]
remove unneeded code

5 years agoreorg setup functions in more add phases
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 10:57:08 +0000 (10:57 +0000)]
reorg setup functions in more add phases

5 years agocleanup modules, however multi-cycle align needs to be like norm1
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 06:03:48 +0000 (06:03 +0000)]
cleanup modules, however multi-cycle align needs to be like norm1

5 years agosplit out single-cycle normalisation to separate module
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 05:39:06 +0000 (05:39 +0000)]
split out single-cycle normalisation to separate module

5 years agoenable single-cycle in FP16 test
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 05:38:45 +0000 (05:38 +0000)]
enable single-cycle in FP16 test

5 years agosingle-shift normalisation right-shift: normalisation now a single-cycle phase
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 04:25:56 +0000 (04:25 +0000)]
single-shift normalisation right-shift: normalisation now a single-cycle phase

5 years agouse MultiShiftRMerge module instead of shift_down_multi function
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 04:13:02 +0000 (04:13 +0000)]
use MultiShiftRMerge module instead of shift_down_multi function

5 years agoremove chain dependence, calculate ediffs in parallel with comparisons
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 02:34:35 +0000 (02:34 +0000)]
remove chain dependence, calculate ediffs in parallel with comparisons

5 years agocomment out unneeded code for now
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 02:26:23 +0000 (02:26 +0000)]
comment out unneeded code for now

5 years agoconvert to only use one multi-shifter
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 02:25:56 +0000 (02:25 +0000)]
convert to only use one multi-shifter

5 years agorename stickybit variable
Luke Kenneth Casson Leighton [Mon, 4 Mar 2019 01:11:10 +0000 (01:11 +0000)]
rename stickybit variable

5 years agounit test for multi-bit shift right with merge (sticky bit)
Luke Kenneth Casson Leighton [Sun, 3 Mar 2019 23:13:51 +0000 (23:13 +0000)]
unit test for multi-bit shift right with merge (sticky bit)

5 years agocleanup
Luke Kenneth Casson Leighton [Sun, 3 Mar 2019 10:12:51 +0000 (10:12 +0000)]
cleanup

5 years agosmall optimisation, move subtraction of -126 from exponent into FPNumBase module...
Luke Kenneth Casson Leighton [Sun, 3 Mar 2019 10:12:04 +0000 (10:12 +0000)]
small optimisation, move subtraction of -126 from exponent into FPNumBase module, use it there and in normalisation

5 years agoadd 3 extra unit tests
Luke Kenneth Casson Leighton [Sun, 3 Mar 2019 09:59:56 +0000 (09:59 +0000)]
add 3 extra unit tests

5 years agolimit count leading zeros to stop exponent shift-amount going below min exp
Luke Kenneth Casson Leighton [Sun, 3 Mar 2019 09:55:44 +0000 (09:55 +0000)]
limit count leading zeros to stop exponent shift-amount going below min exp

5 years agofix shift class syntax errors (untested)
Luke Kenneth Casson Leighton [Sun, 3 Mar 2019 09:52:54 +0000 (09:52 +0000)]
fix shift class syntax errors (untested)

5 years agouse priority encoder for normalisation in single cycle (done decrease)
Luke Kenneth Casson Leighton [Sun, 3 Mar 2019 02:34:20 +0000 (02:34 +0000)]
use priority encoder for normalisation in single cycle (done decrease)

5 years agoadd in FPNumShiftMultiRight class
Luke Kenneth Casson Leighton [Sun, 3 Mar 2019 02:30:59 +0000 (02:30 +0000)]
add in FPNumShiftMultiRight class

5 years agouse bool() function instead of reduce(or_)
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 19:20:25 +0000 (19:20 +0000)]
use bool() function instead of reduce(or_)

5 years agogot single-cycle align working again (accidental combinatorial loop)
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 18:02:20 +0000 (18:02 +0000)]
got single-cycle align working again (accidental combinatorial loop)

5 years agoturn FPOp into module
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 14:13:45 +0000 (14:13 +0000)]
turn FPOp into module

5 years agomove put_z to PutZ class
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 13:58:45 +0000 (13:58 +0000)]
move put_z to PutZ class

5 years agoreorg pack setup
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 13:14:28 +0000 (13:14 +0000)]
reorg pack setup

5 years agoreorg corrections setup
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 13:12:30 +0000 (13:12 +0000)]
reorg corrections setup

5 years agoremove unneeded function call
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 13:10:29 +0000 (13:10 +0000)]
remove unneeded function call

5 years agoremove global z as output from specialcases, use sc.out_z
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 12:56:38 +0000 (12:56 +0000)]
remove global z as output from specialcases, use sc.out_z

5 years agoremove unneeded variable, use module overflow to get rounding signal
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 12:47:46 +0000 (12:47 +0000)]
remove unneeded variable, use module overflow to get rounding signal

5 years agomanaged to make round signal an output from normalisation phase
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 12:42:30 +0000 (12:42 +0000)]
managed to make round signal an output from normalisation phase

5 years agotidyup, remove unneeded intermediate
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 11:22:58 +0000 (11:22 +0000)]
tidyup, remove unneeded intermediate

5 years agotidyup, remove unneeded intermediate
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 11:22:26 +0000 (11:22 +0000)]
tidyup, remove unneeded intermediate

5 years agoreorg FPRound move setup function
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 11:18:56 +0000 (11:18 +0000)]
reorg FPRound move setup function

5 years agoadd comment about add0+add1 stages
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 11:16:05 +0000 (11:16 +0000)]
add comment about add0+add1 stages

5 years agoadd1 module setup reorg
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 11:09:44 +0000 (11:09 +0000)]
add1 module setup reorg

5 years agoremove temporary external z, use add0 output, connect as add1 input
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 11:01:41 +0000 (11:01 +0000)]
remove temporary external z, use add0 output, connect as add1 input

5 years agoreorg: move add0 setup function
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 10:52:52 +0000 (10:52 +0000)]
reorg: move add0 setup function

5 years agouse correct local output from pack chain
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 10:49:54 +0000 (10:49 +0000)]
use correct local output from pack chain

5 years agoreorganise normalisation init: move setup function from mod to class
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 10:46:29 +0000 (10:46 +0000)]
reorganise normalisation init: move setup function from mod to class

5 years agoadd module links (gives useful names)
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 04:00:38 +0000 (04:00 +0000)]
add module links (gives useful names)

5 years agocomplicated way to create a loop inside the normalisation module
Luke Kenneth Casson Leighton [Sat, 2 Mar 2019 03:53:34 +0000 (03:53 +0000)]
complicated way to create a loop inside the normalisation module

5 years agoremove variable overflow
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 22:47:31 +0000 (22:47 +0000)]
remove variable overflow

5 years agoconnect corrections to pack without global z
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 22:31:40 +0000 (22:31 +0000)]
connect corrections to pack without global z

5 years agosplit roundz from norm z
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 22:25:40 +0000 (22:25 +0000)]
split roundz from norm z

5 years agopass add0 z through to add1 independently
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 22:14:02 +0000 (22:14 +0000)]
pass add0 z through to add1 independently

5 years agoadd new temporary z for result chain
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 21:34:49 +0000 (21:34 +0000)]
add new temporary z for result chain

5 years agoconnect add1 to norm1 overflow without global store
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 13:23:34 +0000 (13:23 +0000)]
connect add1 to norm1 overflow without global store

5 years agomerge normalise_1 and normalise_2 stages
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 13:05:24 +0000 (13:05 +0000)]
merge normalise_1 and normalise_2 stages

5 years agocommennt use of intermediates
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 12:01:26 +0000 (12:01 +0000)]
commennt use of intermediates

5 years agostore zero-extended a and b in temp signals
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 11:26:39 +0000 (11:26 +0000)]
store zero-extended a and b in temp signals

5 years agostore tests in temp signals
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 11:20:18 +0000 (11:20 +0000)]
store tests in temp signals

5 years agoexperimenting with chaining Overflow module
Luke Kenneth Casson Leighton [Fri, 1 Mar 2019 09:30:18 +0000 (09:30 +0000)]
experimenting with chaining Overflow module

5 years agouse output from align as input to add0
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 13:15:53 +0000 (13:15 +0000)]
use output from align as input to add0

5 years agoremove commented-out code
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 13:03:02 +0000 (13:03 +0000)]
remove commented-out code

5 years agouse GetOpMod for b
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 13:02:18 +0000 (13:02 +0000)]
use GetOpMod for b

5 years agocreate and use GetOp module
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 12:58:33 +0000 (12:58 +0000)]
create and use GetOp module

5 years agomove fpnum_b to class FPGetB
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 04:42:13 +0000 (04:42 +0000)]
move fpnum_b to class FPGetB

5 years agonarrowing down rounding error to use of Norm1 module
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 03:43:05 +0000 (03:43 +0000)]
narrowing down rounding error to use of Norm1 module

5 years agoseparate denormalisation module and use it
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 03:10:46 +0000 (03:10 +0000)]
separate denormalisation module and use it

5 years agouse denorm exponent signal
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 02:48:45 +0000 (02:48 +0000)]
use denorm exponent signal

5 years agosorting out unit tests, comply with IEEE754 on RISCV
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 00:50:10 +0000 (00:50 +0000)]
sorting out unit tests, comply with IEEE754 on RISCV

5 years agorecompiled sfpy, testing FP16 again
Luke Kenneth Casson Leighton [Thu, 28 Feb 2019 00:13:05 +0000 (00:13 +0000)]
recompiled sfpy, testing FP16 again

5 years agoadd Makefile patches to README
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 23:09:06 +0000 (23:09 +0000)]
add Makefile patches to README

5 years agowhoops, overflow not right, reverting
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 17:18:23 +0000 (17:18 +0000)]
whoops, overflow not right, reverting

5 years agoadd failed test
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 17:14:21 +0000 (17:14 +0000)]
add failed test

5 years agoassign tests to signals
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 17:14:17 +0000 (17:14 +0000)]
assign tests to signals

5 years agocreate single and multi shift cycle, single doesnt work, multi does
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 17:02:50 +0000 (17:02 +0000)]
create single and multi shift cycle, single doesnt work, multi does

5 years agomore chains between inputs and outputs
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 15:34:32 +0000 (15:34 +0000)]
more chains between inputs and outputs

5 years agomove of = Overflow() out of FPADD, use chain
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 15:24:18 +0000 (15:24 +0000)]
move of = Overflow() out of FPADD, use chain

5 years agoremove tot from FPADD, use chain
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 15:04:00 +0000 (15:04 +0000)]
remove tot from FPADD, use chain

5 years agoconnect add0 to add1
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 13:58:51 +0000 (13:58 +0000)]
connect add0 to add1

5 years agocreate add1 stage module and use it
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 13:56:31 +0000 (13:56 +0000)]
create add1 stage module and use it

5 years agotry some more chaining of inputs to outputs
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 13:30:36 +0000 (13:30 +0000)]
try some more chaining of inputs to outputs

5 years agopass output from normalise_2 to input of roundz
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 13:21:22 +0000 (13:21 +0000)]
pass output from normalise_2 to input of roundz

5 years agocreate add0 stage module and use it
Luke Kenneth Casson Leighton [Wed, 27 Feb 2019 13:15:01 +0000 (13:15 +0000)]
create add0 stage module and use it