From 083b06406df21e502efc48d3885a1ca4552c8700 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 6 May 2019 05:12:09 +0100 Subject: [PATCH] LD/ST latches are async (clockless) --- src/scoreboard/ldst_dep_cell.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/scoreboard/ldst_dep_cell.py b/src/scoreboard/ldst_dep_cell.py index ee998e91..f8d62308 100644 --- a/src/scoreboard/ldst_dep_cell.py +++ b/src/scoreboard/ldst_dep_cell.py @@ -35,8 +35,8 @@ class LDSTDepCell(Elaboratable): def elaborate(self, platform): m = Module() - m.submodules.war_l = war_l = SRLatch() # Write After Read Latch - m.submodules.raw_l = raw_l = SRLatch() # Read After Write Latch + m.submodules.war_l = war_l = SRLatch(sync=False) # WriteAfterRead Latch + m.submodules.raw_l = raw_l = SRLatch(sync=False) # ReadAfterWrite Latch # issue & store & load - used for both WAR and RAW Setting i_s_l = Signal(reset_less=True) -- 2.30.2