From 43c4c718784864113e97c08925524359fe52af4b Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 4 May 2019 02:18:11 +0100 Subject: [PATCH] add function unit read/write pending --- src/scoreboard/dependence_cell.py | 10 +++++----- src/scoreboard/fu_wr_pending.py | 20 ++++++++++++++++++++ src/scoreboard/reg_select.py | 3 ++- 3 files changed, 27 insertions(+), 6 deletions(-) create mode 100644 src/scoreboard/fu_wr_pending.py diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py index 3624d1a4..1c8a0095 100644 --- a/src/scoreboard/dependence_cell.py +++ b/src/scoreboard/dependence_cell.py @@ -45,15 +45,15 @@ class DependenceCell(Elaboratable): m.d.sync += src2_l.r.eq(self.go_read_i) # FU "Forward Progress" (read out horizontally) - m.d.comb += self.dest_rsel_o.eq(dest_l.qn & self.go_write_i) - m.d.comb += self.src1_rsel_o.eq(src1_l.qn & self.go_read_i) - m.d.comb += self.src2_rsel_o.eq(src2_l.qn & self.go_read_i) - - # Register File Select (read out vertically) m.d.comb += self.dest_fwd_o.eq(dest_l.qn & self.dest_i) m.d.comb += self.src1_fwd_o.eq(src1_l.qn & self.src1_i) m.d.comb += self.src2_fwd_o.eq(src2_l.qn & self.src2_i) + # Register File Select (read out vertically) + m.d.comb += self.dest_rsel_o.eq(dest_l.qn & self.go_write_i) + m.d.comb += self.src1_rsel_o.eq(src1_l.qn & self.go_read_i) + m.d.comb += self.src2_rsel_o.eq(src2_l.qn & self.go_read_i) + return m def __iter__(self): diff --git a/src/scoreboard/fu_wr_pending.py b/src/scoreboard/fu_wr_pending.py new file mode 100644 index 00000000..9bba20e2 --- /dev/null +++ b/src/scoreboard/fu_wr_pending.py @@ -0,0 +1,20 @@ +from nmigen import Elaboratable, Module, Signal + + +class FUReadWritePending(Elaboratable): + def __init__(self, reg_count): + self.reg_count = reg_count + self.dest_fwd_i = Signal(fu_count, reset_less=True) + self.src1_fwd_i = Signal(fu_count, reset_less=True) + self.src2_fwd_i = Signal(fu_count, reset_less=True) + + self.wr_pend_o = Signal(reset_less=True) + self.rd_pend_o = Signal(reset_less=True) + + def elaboratable(self, platform): + m = Module() + srces = Cat(self.src1_fwd_i, self.src2_fwd_i) + m.d.comb += self.wr_pend_o.eq(self.dest_fwd_i.bool()) + m.d.comb += self.rd_pend_o.eq(srces.bool() + return m + diff --git a/src/scoreboard/reg_select.py b/src/scoreboard/reg_select.py index 9d16741b..04deaac5 100644 --- a/src/scoreboard/reg_select.py +++ b/src/scoreboard/reg_select.py @@ -1,4 +1,5 @@ -from nmigen import Elaboratable, Module, Array, Signal +from nmigen import Elaboratable, Module, Signal + class RegReservation(Elaboratable): def __init__(self, fu_count): -- 2.30.2