From 5ca9e3ee685a261fbff9998ab37940aa3255b9fa Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 14 Mar 2019 03:04:33 +0000 Subject: [PATCH] replace copy of FPState with import of FPState --- src/add/fmul.py | 21 +-------------------- 1 file changed, 1 insertion(+), 20 deletions(-) diff --git a/src/add/fmul.py b/src/add/fmul.py index 0629ffb5..46ad8099 100644 --- a/src/add/fmul.py +++ b/src/add/fmul.py @@ -2,24 +2,7 @@ from nmigen import Module, Signal, Cat, Mux, Array, Const from nmigen.cli import main, verilog from fpbase import FPNum, FPOp, Overflow, FPBase - -class FPState(FPBase): - def __init__(self, state_from): - self.state_from = state_from - - def set_inputs(self, inputs): - self.inputs = inputs - for k,v in inputs.items(): - setattr(self, k, v) - - def set_outputs(self, outputs): - self.outputs = outputs - for k,v in outputs.items(): - setattr(self, k, v) - -''' - -# OLD DESIGN # +from nmigen_add_experiment import FPState class FPMUL(FPBase): @@ -169,5 +152,3 @@ class FPMUL(FPBase): if __name__ == "__main__": alu = FPMUL(width=32) main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports()) - -''' -- 2.30.2