From c41d159271ab6428bb83052795e45737a3a64e70 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 3 May 2019 23:57:08 +0100 Subject: [PATCH] add (synchronous) latch --- src/ieee754/{add => fpadd}/fadd_state.py | 0 src/nmutil/latch.py | 53 ++++++++++++++++++++++++ 2 files changed, 53 insertions(+) rename src/ieee754/{add => fpadd}/fadd_state.py (100%) create mode 100644 src/nmutil/latch.py diff --git a/src/ieee754/add/fadd_state.py b/src/ieee754/fpadd/fadd_state.py similarity index 100% rename from src/ieee754/add/fadd_state.py rename to src/ieee754/fpadd/fadd_state.py diff --git a/src/nmutil/latch.py b/src/nmutil/latch.py new file mode 100644 index 00000000..7c59b983 --- /dev/null +++ b/src/nmutil/latch.py @@ -0,0 +1,53 @@ +from nmigen.compat.sim import run_simulation +from nmigen.cli import verilog, rtlil +from nmigen import Signal, Module, Elaboratable + + +class SRLatch(Elaboratable): + def __init__(self): + self.s = Signal(reset_less=True) + self.r = Signal(reset_less=True) + self.q = Signal(reset_less=True) + self.qn = Signal(reset_less=True) + + def elaborate(self, platform): + m = Module() + q_int = Signal(reset_less=True) + qn_int = Signal(reset_less=True) + + m.d.comb += self.q.eq(~(self.s | qn_int)) + m.d.comb += self.qn.eq(~(self.r | q_int)) + + m.d.sync += q_int.eq(self.q) + m.d.sync += qn_int.eq(self.qn) + + return m + + def ports(self): + return self.s, self.r, self.q, self.qn + + +def sr_sim(dut): + yield dut.s.eq(0) + yield dut.r.eq(0) + yield + yield dut.s.eq(1) + yield + yield dut.s.eq(0) + yield + yield dut.r.eq(1) + yield + yield dut.r.eq(0) + yield + yield + +def test_sr(): + dut = SRLatch() + vl = rtlil.convert(dut, ports=dut.ports()) + with open("test_srlatch.il", "w") as f: + f.write(vl) + + run_simulation(dut, sr_sim(dut), vcd_name='test_srlatch.vcd') + +if __name__ == '__main__': + test_sr() -- 2.30.2