From f09f35af37956dc1e3cc01aadc84ad07a711d2d4 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 2 May 2019 15:34:30 +0100 Subject: [PATCH] more code-shuffle --- src/ieee754/add/concurrentunit.py | 7 ------- src/ieee754/add/dual_add_experiment.py | 2 +- src/ieee754/add/fadd_state.py | 2 +- src/ieee754/add/inputgroup.py | 2 +- src/ieee754/add/rstation_row.py | 4 ++-- src/ieee754/add/test_fpnum.py | 2 +- src/ieee754/add/test_fsm_experiment.py | 2 +- src/ieee754/add/test_multishift.py | 2 +- src/ieee754/fpadd/add0.py | 4 ++-- src/ieee754/fpadd/add1.py | 2 +- src/ieee754/fpadd/addstages.py | 2 +- src/ieee754/fpadd/align.py | 6 +++--- src/ieee754/fpadd/specialcases.py | 4 ++-- src/ieee754/fpadd/statemachine.py | 6 +++--- src/ieee754/fpcommon/corrections.py | 2 +- src/ieee754/fpcommon/denorm.py | 4 ++-- src/ieee754/fpcommon/fpbase.py | 2 +- src/ieee754/fpcommon/getop.py | 6 +++--- src/ieee754/fpcommon/normtopack.py | 2 +- src/ieee754/fpcommon/pack.py | 4 ++-- src/ieee754/fpcommon/postcalc.py | 2 +- src/ieee754/fpcommon/postnormalise.py | 6 +++--- src/ieee754/fpcommon/prenormalise.py | 6 +++--- src/ieee754/fpcommon/putz.py | 2 +- src/ieee754/fpcommon/roundz.py | 4 ++-- src/ieee754/fpdiv/nmigen_div_experiment.py | 2 +- src/ieee754/fpmul/fmul.py | 2 +- src/nmutil/multipipe.py | 4 +++- 28 files changed, 45 insertions(+), 50 deletions(-) diff --git a/src/ieee754/add/concurrentunit.py b/src/ieee754/add/concurrentunit.py index 9419d528..82b81ff5 100644 --- a/src/ieee754/add/concurrentunit.py +++ b/src/ieee754/add/concurrentunit.py @@ -10,13 +10,6 @@ from nmutil.singlepipe import PassThroughStage from nmutil.multipipe import CombMuxOutPipe from nmutil.multipipe import PriorityCombMuxInPipe -from ieee754.fpcommon.getop import FPADDBaseData -from ieee754.fpcommon.denorm import FPSCData -from ieee754.fpcommon.pack import FPPackData -from ieee754.fpcommon.normtopack import FPNormToPack -from ieee754.fpadd.specialcases import FPAddSpecialCasesDeNorm -from ieee754.fpadd.addstages import FPAddAlignSingleAdd - def num_bits(n): return int(log(n) / log(2)) diff --git a/src/ieee754/add/dual_add_experiment.py b/src/ieee754/add/dual_add_experiment.py index 7ec479f5..8c663ef1 100644 --- a/src/ieee754/add/dual_add_experiment.py +++ b/src/ieee754/add/dual_add_experiment.py @@ -2,7 +2,7 @@ from nmigen import * from nmigen.cli import main from nmigen_add_experiment import FPADD -from fpbase import FPOp +from ieee754.fpcommon.fpbase import FPOp class Adder: diff --git a/src/ieee754/add/fadd_state.py b/src/ieee754/add/fadd_state.py index be4f7d57..2c088421 100644 --- a/src/ieee754/add/fadd_state.py +++ b/src/ieee754/add/fadd_state.py @@ -5,7 +5,7 @@ from nmigen import Module, Signal, Cat from nmigen.cli import main, verilog -from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase +from ieee754.fpcommon.fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase from nmutil.singlepipe import eq diff --git a/src/ieee754/add/inputgroup.py b/src/ieee754/add/inputgroup.py index e1b775d4..9322c8a1 100644 --- a/src/ieee754/add/inputgroup.py +++ b/src/ieee754/add/inputgroup.py @@ -2,7 +2,7 @@ from nmigen import Module, Signal, Cat, Array, Const from nmigen.lib.coding import PriorityEncoder from math import log -from fpbase import Trigger +from ieee754.fpcommon.fpbase import Trigger class FPGetSyncOpsMod: diff --git a/src/ieee754/add/rstation_row.py b/src/ieee754/add/rstation_row.py index aeb58732..63eaac2e 100644 --- a/src/ieee754/add/rstation_row.py +++ b/src/ieee754/add/rstation_row.py @@ -2,8 +2,8 @@ from nmigen import Signal, Cat, Const, Mux, Module from nmigen.cli import main, verilog -from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase -from fpbase import MultiShiftRMerge +from ieee754.fpcommon.fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase +from ieee754.fpcommon.fpbase import MultiShiftRMerge class ReservationStationRow: diff --git a/src/ieee754/add/test_fpnum.py b/src/ieee754/add/test_fpnum.py index 6d9ecd10..1d018b3f 100644 --- a/src/ieee754/add/test_fpnum.py +++ b/src/ieee754/add/test_fpnum.py @@ -2,7 +2,7 @@ from random import randint from nmigen import Module, Signal from nmigen.compat.sim import run_simulation -from fpbase import FPNum +from ieee754.fpcommon.fpbase import FPNum class FPNumModShiftMulti: def __init__(self, width): diff --git a/src/ieee754/add/test_fsm_experiment.py b/src/ieee754/add/test_fsm_experiment.py index 1a338f56..204a7d18 100644 --- a/src/ieee754/add/test_fsm_experiment.py +++ b/src/ieee754/add/test_fsm_experiment.py @@ -7,7 +7,7 @@ from nmigen.cli import main, verilog, rtlil from nmigen.compat.sim import run_simulation -from fpbase import FPNumIn, FPNumOut, FPOpIn, FPOpOut, FPBase, FPState +from ieee754.fpcommon.fpbase import FPNumIn, FPNumOut, FPOpIn, FPOpOut, FPBase, FPState from nmutil.nmoperator import eq from nmutil.singlepipe import SimpleHandshake, ControlBase from test_buf_pipe import data_chain2, Test5 diff --git a/src/ieee754/add/test_multishift.py b/src/ieee754/add/test_multishift.py index 651e5018..86483453 100644 --- a/src/ieee754/add/test_multishift.py +++ b/src/ieee754/add/test_multishift.py @@ -2,7 +2,7 @@ from random import randint from nmigen import Module, Signal from nmigen.compat.sim import run_simulation -from fpbase import MultiShift, MultiShiftR, MultiShiftRMerge +from ieee754.fpcommon.fpbase import MultiShift, MultiShiftR, MultiShiftRMerge class MultiShiftModL: def __init__(self, width): diff --git a/src/ieee754/fpadd/add0.py b/src/ieee754/fpadd/add0.py index f380d3e5..db04506c 100644 --- a/src/ieee754/fpadd/add0.py +++ b/src/ieee754/fpadd/add0.py @@ -5,8 +5,8 @@ from nmigen import Module, Signal, Cat, Elaboratable from nmigen.cli import main, verilog -from fpbase import FPNumBase -from fpbase import FPState +from ieee754.fpcommon.fpbase import FPNumBase +from ieee754.fpcommon.fpbase import FPState from ieee754.fpcommon.denorm import FPSCData diff --git a/src/ieee754/fpadd/add1.py b/src/ieee754/fpadd/add1.py index 1c0ff27a..12054312 100644 --- a/src/ieee754/fpadd/add1.py +++ b/src/ieee754/fpadd/add1.py @@ -6,7 +6,7 @@ from nmigen import Module, Signal, Elaboratable from nmigen.cli import main, verilog from math import log -from fpbase import FPState +from ieee754.fpcommon.fpbase import FPState from ieee754.fpcommon.postcalc import FPAddStage1Data from .add0 import FPAddStage0Data diff --git a/src/ieee754/fpadd/addstages.py b/src/ieee754/fpadd/addstages.py index b373f1e3..b398a274 100644 --- a/src/ieee754/fpadd/addstages.py +++ b/src/ieee754/fpadd/addstages.py @@ -8,7 +8,7 @@ from nmigen.cli import main, verilog from nmutil.singlepipe import (StageChain, SimpleHandshake, PassThroughStage) -from fpbase import FPState +from ieee754.fpcommon.fpbase import FPState from ieee754.fpcommon.denorm import FPSCData from ieee754.fpcommon.postcalc import FPAddStage1Data from .align import FPAddAlignSingleMod diff --git a/src/ieee754/fpadd/align.py b/src/ieee754/fpadd/align.py index c4b4d52f..381df1e5 100644 --- a/src/ieee754/fpadd/align.py +++ b/src/ieee754/fpadd/align.py @@ -5,9 +5,9 @@ from nmigen import Module, Signal from nmigen.cli import main, verilog -from fpbase import FPNumOut, FPNumIn, FPNumBase -from fpbase import MultiShiftRMerge -from fpbase import FPState +from ieee754.fpcommon.fpbase import FPNumOut, FPNumIn, FPNumBase +from ieee754.fpcommon.fpbase import MultiShiftRMerge +from ieee754.fpcommon.fpbase import FPState from ieee754.fpcommon.denorm import FPSCData diff --git a/src/ieee754/fpadd/specialcases.py b/src/ieee754/fpadd/specialcases.py index 978851ef..d6dea0ac 100644 --- a/src/ieee754/fpadd/specialcases.py +++ b/src/ieee754/fpadd/specialcases.py @@ -6,10 +6,10 @@ from nmigen import Module, Signal, Cat, Const from nmigen.cli import main, verilog from math import log -from fpbase import FPNumDecode +from ieee754.fpcommon.fpbase import FPNumDecode from nmutil.singlepipe import SimpleHandshake, StageChain -from fpbase import FPState, FPID +from ieee754.fpcommon.fpbase import FPState, FPID from ieee754.fpcommon.getop import FPADDBaseData from ieee754.fpcommon.denorm import (FPSCData, FPAddDeNormMod) diff --git a/src/ieee754/fpadd/statemachine.py b/src/ieee754/fpadd/statemachine.py index 5afe702e..bdcec1ba 100644 --- a/src/ieee754/fpadd/statemachine.py +++ b/src/ieee754/fpadd/statemachine.py @@ -6,11 +6,11 @@ from nmigen import Module, Signal, Cat, Mux, Array, Const from nmigen.cli import main, verilog from math import log -from fpbase import FPOpIn, FPOpOut -from fpbase import Trigger +from ieee754.fpcommon.fpbase import FPOpIn, FPOpOut +from ieee754.fpcommon.fpbase import Trigger from nmutil.singlepipe import (StageChain, SimpleHandshake) -from fpbase import FPState, FPID +from ieee754.fpcommon.fpbase import FPState, FPID from ieee754.fpcommon.getop import (FPGetOp, FPADDBaseData, FPGet2Op) from ieee754.fpcommon.denorm import (FPSCData, FPAddDeNorm) from ieee754.fpcommon.postcalc import FPAddStage1Data diff --git a/src/ieee754/fpcommon/corrections.py b/src/ieee754/fpcommon/corrections.py index 68340275..1405d43d 100644 --- a/src/ieee754/fpcommon/corrections.py +++ b/src/ieee754/fpcommon/corrections.py @@ -4,7 +4,7 @@ from nmigen import Module, Elaboratable from nmigen.cli import main, verilog -from fpbase import FPState +from ieee754.fpcommon.fpbase import FPState from .roundz import FPRoundData diff --git a/src/ieee754/fpcommon/denorm.py b/src/ieee754/fpcommon/denorm.py index 9fbbc976..cf54b0f3 100644 --- a/src/ieee754/fpcommon/denorm.py +++ b/src/ieee754/fpcommon/denorm.py @@ -6,8 +6,8 @@ from nmigen import Module, Signal from nmigen.cli import main, verilog from math import log -from fpbase import FPNumIn, FPNumOut, FPNumBase -from fpbase import FPState +from ieee754.fpcommon.fpbase import FPNumIn, FPNumOut, FPNumBase +from ieee754.fpcommon.fpbase import FPState class FPSCData: diff --git a/src/ieee754/fpcommon/fpbase.py b/src/ieee754/fpcommon/fpbase.py index dbd4da27..ffecd2fd 100644 --- a/src/ieee754/fpcommon/fpbase.py +++ b/src/ieee754/fpcommon/fpbase.py @@ -8,7 +8,7 @@ from operator import or_ from functools import reduce from nmutil.singlepipe import PrevControl, NextControl -from pipeline import ObjectProxy +from nmutil.pipeline import ObjectProxy class MultiShiftR: diff --git a/src/ieee754/fpcommon/getop.py b/src/ieee754/fpcommon/getop.py index f772d904..b534fd0a 100644 --- a/src/ieee754/fpcommon/getop.py +++ b/src/ieee754/fpcommon/getop.py @@ -7,14 +7,14 @@ from nmigen.lib.coding import PriorityEncoder from nmigen.cli import main, verilog from math import log -from fpbase import FPNumIn, FPNumOut, FPOpIn, Overflow, FPBase, FPNumBase -from fpbase import MultiShiftRMerge, Trigger +from ieee754.fpcommon.fpbase import FPNumIn, FPNumOut, FPOpIn, Overflow, FPBase, FPNumBase +from ieee754.fpcommon.fpbase import MultiShiftRMerge, Trigger from nmutil.singlepipe import (ControlBase, StageChain, SimpleHandshake, PassThroughStage, PrevControl) from nmutil.multipipe import CombMuxOutPipe from nmutil.multipipe import PriorityCombMuxInPipe -from fpbase import FPState +from ieee754.fpcommon.fpbase import FPState from nmutil import nmoperator diff --git a/src/ieee754/fpcommon/normtopack.py b/src/ieee754/fpcommon/normtopack.py index ac97bf1c..9cba7255 100644 --- a/src/ieee754/fpcommon/normtopack.py +++ b/src/ieee754/fpcommon/normtopack.py @@ -6,7 +6,7 @@ from nmutil.singlepipe import StageChain, SimpleHandshake -from fpbase import FPState, FPID +from ieee754.fpcommon.fpbase import FPState, FPID from .postcalc import FPAddStage1Data from .postnormalise import FPNorm1ModSingle from .roundz import FPRoundMod diff --git a/src/ieee754/fpcommon/pack.py b/src/ieee754/fpcommon/pack.py index 7407cfb6..1042b1b0 100644 --- a/src/ieee754/fpcommon/pack.py +++ b/src/ieee754/fpcommon/pack.py @@ -5,8 +5,8 @@ from nmigen import Module, Signal, Elaboratable from nmigen.cli import main, verilog -from fpbase import FPNumOut -from fpbase import FPState +from ieee754.fpcommon.fpbase import FPNumOut +from ieee754.fpcommon.fpbase import FPState from .roundz import FPRoundData from nmutil.singlepipe import Object diff --git a/src/ieee754/fpcommon/postcalc.py b/src/ieee754/fpcommon/postcalc.py index 7111dc8a..92e8713d 100644 --- a/src/ieee754/fpcommon/postcalc.py +++ b/src/ieee754/fpcommon/postcalc.py @@ -3,7 +3,7 @@ # 2013-12-12 from nmigen import Signal -from fpbase import Overflow, FPNumBase +from ieee754.fpcommon.fpbase import Overflow, FPNumBase class FPAddStage1Data: diff --git a/src/ieee754/fpcommon/postnormalise.py b/src/ieee754/fpcommon/postnormalise.py index b072490f..48124184 100644 --- a/src/ieee754/fpcommon/postnormalise.py +++ b/src/ieee754/fpcommon/postnormalise.py @@ -7,9 +7,9 @@ from nmigen.lib.coding import PriorityEncoder from nmigen.cli import main, verilog from math import log -from fpbase import Overflow, FPNumBase -from fpbase import MultiShiftRMerge -from fpbase import FPState +from ieee754.fpcommon.fpbase import Overflow, FPNumBase +from ieee754.fpcommon.fpbase import MultiShiftRMerge +from ieee754.fpcommon.fpbase import FPState from .postcalc import FPAddStage1Data diff --git a/src/ieee754/fpcommon/prenormalise.py b/src/ieee754/fpcommon/prenormalise.py index 0b3a65cb..83d6f6d0 100644 --- a/src/ieee754/fpcommon/prenormalise.py +++ b/src/ieee754/fpcommon/prenormalise.py @@ -7,10 +7,10 @@ from nmigen.lib.coding import PriorityEncoder from nmigen.cli import main, verilog from math import log -from fpbase import Overflow, FPNumBase -from fpbase import MultiShiftRMerge +from ieee754.fpcommon.fpbase import Overflow, FPNumBase +from ieee754.fpcommon.fpbase import MultiShiftRMerge -from fpbase import FPState +from ieee754.fpcommon.fpbase import FPState class FPNormaliseModSingle: diff --git a/src/ieee754/fpcommon/putz.py b/src/ieee754/fpcommon/putz.py index 8173ed85..b07ac85a 100644 --- a/src/ieee754/fpcommon/putz.py +++ b/src/ieee754/fpcommon/putz.py @@ -4,7 +4,7 @@ from nmigen import Signal from nmigen.cli import main, verilog -from fpbase import FPState +from ieee754.fpcommon.fpbase import FPState class FPPutZ(FPState): diff --git a/src/ieee754/fpcommon/roundz.py b/src/ieee754/fpcommon/roundz.py index 2b456fba..130c5ec2 100644 --- a/src/ieee754/fpcommon/roundz.py +++ b/src/ieee754/fpcommon/roundz.py @@ -5,8 +5,8 @@ from nmigen import Module, Signal, Elaboratable from nmigen.cli import main, verilog -from fpbase import FPNumBase -from fpbase import FPState +from ieee754.fpcommon.fpbase import FPNumBase +from ieee754.fpcommon.fpbase import FPState from .postnormalise import FPNorm1Data diff --git a/src/ieee754/fpdiv/nmigen_div_experiment.py b/src/ieee754/fpdiv/nmigen_div_experiment.py index a19decd5..7887a527 100644 --- a/src/ieee754/fpdiv/nmigen_div_experiment.py +++ b/src/ieee754/fpdiv/nmigen_div_experiment.py @@ -5,7 +5,7 @@ from nmigen import Module, Signal, Const, Cat from nmigen.cli import main, verilog -from fpbase import FPNumIn, FPNumOut, FPOpIn, FPOpOut, Overflow, FPBase, FPState +from ieee754.fpcommon.fpbase import FPNumIn, FPNumOut, FPOpIn, FPOpOut, Overflow, FPBase, FPState from nmutil.singlepipe import eq class Div: diff --git a/src/ieee754/fpmul/fmul.py b/src/ieee754/fpmul/fmul.py index abe6f613..3ad9e539 100644 --- a/src/ieee754/fpmul/fmul.py +++ b/src/ieee754/fpmul/fmul.py @@ -1,7 +1,7 @@ from nmigen import Module, Signal, Cat, Mux, Array, Const from nmigen.cli import main, verilog -from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPState +from ieee754.fpcommon.fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPState from fpcommon.getop import FPGetOp from nmutil.singlepipe import eq diff --git a/src/nmutil/multipipe.py b/src/nmutil/multipipe.py index 04ab6f7e..efc1e005 100644 --- a/src/nmutil/multipipe.py +++ b/src/nmutil/multipipe.py @@ -19,7 +19,8 @@ from nmutil.stageapi import _spec from collections.abc import Sequence -from example_buf_pipe import eq, NextControl, PrevControl, ExampleStage +from .nmoperator import eq +from .iocontrol import NextControl, PrevControl class MultiInControlBase(Elaboratable): @@ -352,6 +353,7 @@ class PriorityCombMuxInPipe(CombMultiInPipeline): if __name__ == '__main__': + from nmutil.test.example_buf_pipe import ExampleStage dut = PriorityCombMuxInPipe(ExampleStage) vl = rtlil.convert(dut, ports=dut.ports()) with open("test_combpipe.il", "w") as f: -- 2.30.2