bug 1244: add assembler and python maxloc listing to slides

[libreriscv.git] / conferences / fosdem2024 / fosdem2024_ddffirst / maxloc.s

diff --git a/conferences/fosdem2024/fosdem2024_ddffirst/maxloc.s b/conferences/fosdem2024/fosdem2024_ddffirst/maxloc.s
index f94ebb7f253fa6b23af277cb2393f555fee4ec82..f72de742ada525b7e148fb4dedffa11faf37d2fa 100644 (file)
--- a/conferences/fosdem2024/fosdem2024_ddffirst/maxloc.s
+++ b/conferences/fosdem2024/fosdem2024_ddffirst/maxloc.s
@@ -1,15 +1,15 @@
 # while (i<n)
-setvl 2,0,4,0,1,1            # set MVL=4, VL=MIN(MVL,CTR)
-#    while (i<n and a[i]<=m) : i += 1
+setvl 2,0,4,0,1,1     # set MVL=4,VL=MIN(MVL,CTR)
+#  while (i<n and a[i]<=m) : i += 1
 sv.cmp/ff=gt/m=ge *0,0,*10,4 # truncates VL to min
-sv.creqv *16,*16,*16         # set mask on already-tested
-setvl 2,0,4,0,1,1            # set MVL=4, VL=MIN(MVL,CTR)
-mtcrf 128, 0                 # clear CR0 (in case VL=0?)
-#    while (i<n and a[i]>m):
-sv.minmax./ff=le/m=ge/mr 4,*10,4,1 # r4 accumulator
-crternlogi 0,1,2,127         # test greater/equal or VL=0
-sv.crand *19,*16,0           # clear if CR0.eq=0
-#      nm = i (count masked bits. could use crweirds here)
-sv.svstep/mr/m=so 1,0,6,1    # svstep: get vector dststep
-sv.creqv *16,*16,*16         # set mask on already-tested
-bc 12,0, -0x40               # CR0 lt bit clear, branch back
+sv.creqv *16,*16,*16  # set mask on already-tested
+setvl 2,0,4,0,1,1     # set MVL=4,VL=MIN(MVL,CTR)
+mtcrf 128,0           # clear CR0 (in case VL=0?)
+#  while (i<n and a[i]>m):
+sv.minmax./ff=le/m=ge/mr 4,*10,4,1 # r4 accumulate
+crternlogi 0,1,2,127  # test >= (or VL=0)
+sv.crand *19,*16,0    # clear if CR0.eq=0
+#   nm = i: count masked bits. could use crweirds
+sv.svstep/mr/m=so 1,0,6,1 # get vector dststep
+sv.creqv *16,*16,*16  # set mask on already-tested
+bc 12,0,-0x40         # CR0 lt clear, branch back