From 0d6c999786c884c4a234b96a3036dafc8c496aa9 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 12 Feb 2024 17:46:55 +0000 Subject: [PATCH] bug 1244: add maxloc.s and maxloc.py --- .../fosdem2024_ddffirst/fosdem2024_ddffirst.tex | 1 + .../fosdem2024/fosdem2024_ddffirst/maxloc.py | 5 +++++ .../fosdem2024/fosdem2024_ddffirst/maxloc.s | 15 +++++++++++++++ 3 files changed, 21 insertions(+) create mode 100644 conferences/fosdem2024/fosdem2024_ddffirst/maxloc.py create mode 100644 conferences/fosdem2024/fosdem2024_ddffirst/maxloc.s diff --git a/conferences/fosdem2024/fosdem2024_ddffirst/fosdem2024_ddffirst.tex b/conferences/fosdem2024/fosdem2024_ddffirst/fosdem2024_ddffirst.tex index 30c79c5f9..3317021a8 100644 --- a/conferences/fosdem2024/fosdem2024_ddffirst/fosdem2024_ddffirst.tex +++ b/conferences/fosdem2024/fosdem2024_ddffirst/fosdem2024_ddffirst.tex @@ -260,6 +260,7 @@ for (i = 0; i < VL; i++) \item http://libre-soc.org/ \item https://nlnet.nl/project/Libre-SOC-OpenPOWER-ISA \item https://bugs.libre-soc.org/show\_bug.cgi?id=676 +\item https://bugs.libre-soc.org/show\_bug.cgi?id=1244 \item https://libre-soc.org/openpower/sv/cookbook/fortran\_maxloc \item https://libre-soc.org/nlnet/\#faq \end{itemize} diff --git a/conferences/fosdem2024/fosdem2024_ddffirst/maxloc.py b/conferences/fosdem2024/fosdem2024_ddffirst/maxloc.py new file mode 100644 index 000000000..031ffc33d --- /dev/null +++ b/conferences/fosdem2024/fosdem2024_ddffirst/maxloc.py @@ -0,0 +1,5 @@ + +m,nm,i,n = 0,0,0,len(a) +while (i m): m,nm,i = a[i],i,i+1 diff --git a/conferences/fosdem2024/fosdem2024_ddffirst/maxloc.s b/conferences/fosdem2024/fosdem2024_ddffirst/maxloc.s new file mode 100644 index 000000000..f94ebb7f2 --- /dev/null +++ b/conferences/fosdem2024/fosdem2024_ddffirst/maxloc.s @@ -0,0 +1,15 @@ +# while (im): +sv.minmax./ff=le/m=ge/mr 4,*10,4,1 # r4 accumulator +crternlogi 0,1,2,127 # test greater/equal or VL=0 +sv.crand *19,*16,0 # clear if CR0.eq=0 +# nm = i (count masked bits. could use crweirds here) +sv.svstep/mr/m=so 1,0,6,1 # svstep: get vector dststep +sv.creqv *16,*16,*16 # set mask on already-tested +bc 12,0, -0x40 # CR0 lt bit clear, branch back -- 2.30.2