From 79d5d5b58b9fa65ad6c8e39e6380ac33c0cf723b Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 17 Feb 2024 23:46:14 +0000 Subject: [PATCH] --- nlnet_2023_simplev_riscv_binutils.mdwn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/nlnet_2023_simplev_riscv_binutils.mdwn b/nlnet_2023_simplev_riscv_binutils.mdwn index 0cbeceddb..97c835382 100644 --- a/nlnet_2023_simplev_riscv_binutils.mdwn +++ b/nlnet_2023_simplev_riscv_binutils.mdwn @@ -20,7 +20,8 @@ Please be short and to the point in your answers; focus primarily on the what an ## Abstract: Can you explain the whole project and its expected outcome(s). -This project is to enhance binutils tools to continue the autogenerated supportfor the +This project is to enhance binutils tools to continue the autogenerated support +for the RISC-V, Power and other ISAs, and to also support Simple-V Vectorisation capabilities. It will directly support the ISA Expansion project @@ -51,7 +52,7 @@ Key phases of this project are: and SVP64/Power (currently based on an early iteration of libopid) * Definition of assembler and disassembler for RISC-V instructions and also SVP32, 48 and 64 Vector Prefixing formats, using libopid -* Completion of definitions of Simple-V/Single formats SVP64Single, SVP48Singe and SVP32Single +* Completion of definitions of Simple-V/Single formats SVP64Single, SVP48Single and SVP32Single and implementation support of the same for both Power and RISC-V (https://libre-soc.org/openpower/sv/svp64-single/) * Test vectors for libopid and binutils -- 2.30.2