From d643960f83ba91215f0d007daddb4a15eed03b8b Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 7 Feb 2024 20:16:08 +0000
Subject: [PATCH] note update date on RFC ls004 (v2)

---
 openpower/sv/rfc/ls004.mdwn | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/openpower/sv/rfc/ls004.mdwn b/openpower/sv/rfc/ls004.mdwn
index cdb114e46..4fcf6577c 100644
--- a/openpower/sv/rfc/ls004.mdwn
+++ b/openpower/sv/rfc/ls004.mdwn
@@ -1,4 +1,4 @@
-# RFC ls004  Shift-And-Add
+# RFC ls004 v2 Shift-And-Add and LD/ST-Shifted
 
 * Funded by NLnet under the Privacy and Enhanced Trust Programme, EU
   Horizon2020 Grant 825310, and NGI0 Entrust No 101069594
@@ -16,7 +16,7 @@
 
 **Status**: New
 
-**Date**: 31 Oct 2022
+**Date**: 07 Feb 2024
 
 **Target**: v3.2B
 
@@ -39,7 +39,7 @@
     sadd - Shift and Add
     saddw - Shift and Add Signed Word
     sadduw - Shift and Add Unsigned Word
-    Also under consideration LD/ST-Indexed-Shifted
+    Also LD/ST-Indexed-Shifted (Fixed and Floating)
 ```
 
 **Submitter**: Luke Leighton (Libre-SOC)
@@ -70,6 +70,7 @@
 Power ISA is missing LD/ST Indexed with shift, which is present in both ARM
 and x86.  Adding more LD/ST is thirty eight instructions, a compromise is to
 add shift-and-add.  Replaces a pair of explicit instructions in hot-loops.
+Adding actual LD/ST Shifted saves even further.
 
 **Notes and Observations**:
 
-- 
2.30.2