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(parent: 47083f3) | patch
First setup for cocotb test run.
authorStaf Verhaegen <staf@stafverhaegen.be>
Thu, 1 Apr 2021 11:23:04 +0000 (13:23 +0200)
committerStaf Verhaegen <staf@stafverhaegen.be>
Thu, 1 Apr 2021 11:23:04 +0000 (13:23 +0200)
commit3e69d2095ab2e0dd64fe94ca1547ecc8a2f56719
tree44e919871c1d68447efdbcc3db2514b9f5228fc7tree
parent47083f3531935d83fd1dfe98faf465cad8804cffcommit | diff
First setup for cocotb test run.

Currently only test bench is using Icarus Verilog on pre-layout design
without SRAMs.
cocotb/Makefile [new file with mode: 0644] blob
cocotb/README.md [new file with mode: 0644] blob
cocotb/clean.sh [new file with mode: 0755] blob
cocotb/idcode.svf [new file with mode: 0644] blob
cocotb/run_iverilog.sh [new file with mode: 0755] blob
cocotb/test.py [new file with mode: 0644] blob