sort out PLL connection, in and out of peripheral interconnect
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 9 Jun 2021 15:50:54 +0000 (16:50 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 9 Jun 2021 15:50:54 +0000 (16:50 +0100)
commit7d251f1b58cb3e1d5788645b4ce38286d6814c04
tree64b443b3504f1c793a13fbcf3b108f450f0c81e1
parent6f31d65eb4433b66d64fcf924f2c0eb3cb4b9b3b
sort out PLL connection, in and out of peripheral interconnect
libresoc/core.py
libresoc/ls180.py
ls180soc.py