Revert "Wire up missing CRG / DDR3 clock control / reset signals"
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 10 Apr 2022 17:15:35 +0000 (18:15 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 10 Apr 2022 17:15:35 +0000 (18:15 +0100)
commit1fed7eb28605c7498cd44672ebae37eae2a96ac7
tree76b5ad57eb7504ecb2a556b23d5924508618cc4b
parent123690d57b4ae3b4ff76cdc73f5cde5a333ad3a2
Revert "Wire up missing CRG / DDR3 clock control / reset signals"

This reverts commit 19ed0026e91b2dd351fbd2d692fb2c6f45b42622.
src/ecp5_crg.py
src/ls2.py