put versa_ecp5 below 50 mhz as a bodge-way to stop it trying

put versa_ecp5 below 50 mhz as a bodge-way to stop it trying
to create a DDR3 peripheral.  this then activates placing an SRAM (BRAM)
at 0x0000_0000 of size 0x8000 which can be used for a micro-test of
booting from QSPI.
and 0x8000 SRAM is much easier to simulate in icarus verilog