add default args in DDR3SoC
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 14 Apr 2022 15:38:54 +0000 (16:38 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 14 Apr 2022 15:38:54 +0000 (16:38 +0100)
commit96dc900e690e68e465b0ef92455935d6bb6bf8a3
treee65a632125ffaaa51a2affbd8144e26b3be6050e
parent682a21dbfdedb696388ce89e64719df284d223ff
add default args in DDR3SoC
src/ls2.py