execute1: Improve timing on comparisons
authorPaul Mackerras <paulus@ozlabs.org>
Mon, 28 Sep 2020 04:04:08 +0000 (14:04 +1000)
committerPaul Mackerras <paulus@ozlabs.org>
Fri, 15 Jan 2021 01:40:54 +0000 (12:40 +1100)
commitf7b855dfc36cd1d916e019ab31edbcc679077255
treeb024323ba58b5f6bac22fd1469f57301b75499d5
parentb0510fd1bbfe50ab7f61e6be4a4643c9d5dd87b1
execute1: Improve timing on comparisons

Using the main adder for comparisons has the disadvantage of creating
a long path from the CA/OV bit forwarding to v.busy via the carry
input of the adder, the comparison result, and determining whether a
trap instruction would trap.  Instead we now have dedicated
comparators for the high and low words of a_in vs. b_in, and combine
their results to get the signed and unsigned comparison results.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
execute1.vhdl